Intel i960 Jx Developer's Manual page 490

Microprocessor
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TEST FEATURES
Example 15-1. Boundary Scan Description Language Example
AVCC
NC
use STD_1149_1_1990.all;
use i960JX_a.all;
--This list describes the physical pin layout of all signals
attribute PIN_MAP of JX_Processor : entity is PHYSICAL_PIN_MAP;
constant PGA_14x14 : PIN_MAP_STRING :=
"TDI
: F16,"&
"RDYRCVBAR
: E15,"&
"TRSTBAR
: C17,"&
"TCK
: C16,"&
"TMS
: B17,"&
"HOLD
: C15,"&
"XINTBARX
: (B16, C14, B15, C13, B14, A15, A14, C12),"&
"NMIBAR
: B12,"&
"FAILBAR
: B09,"&
"ALEBAR
: C08,"&
"TDO
: CO7,"&
"WIDTH
: (C06, BO6),"&
"A32
: (A04, C05),"&
"BLASTBAR
: BO3,"&
"DCBAR
: C02,"&
"ADSBAR
: C03,"&
"WRBAR
: B01,"&
"DTRBAR
: B02,"&
"DENBAR
: E03,"&
"HOLDA
: D02,"&
"ALE
: C01,"&
"LOCKONCEBAR
: D01,"&
"BSTAT
: F03,"&
"BEBAR
: (E01, E02, G03, H03),"&
"AD
: (P03, R02, Q03, R03, S03, R04, S04, Q05, Q06, Q07,"&
"
"
"
"CLKIN
: J17,"&
"RESETBAR
: G15,"&
"STEST
: F17,"&
"VCC
: (S13, S12, S11, S10, S08, S07, S06, S05, N17, M17," &
"
"
"VSS
: (R13, R12, R11, R10, R08, R07, R06, R05, N16, N02," &
"
"
"AVCC
: L15 ";
attribute Tap_Scan_In
attribute Tap_Scan_Mode
attribute Tap_Scan_Out
attribute Tap_Scan_Reset of
attribute Tap_Scan_Clock of
attribute Instruction_Length of JX_Processor: entity is 4;
attribute Instruction_Opcode of JX_Processor: entity is
"BYPASS
(1111)," &
"EXTEST
(0000)," &
"SAMPLE
(0001)," &
"IDCODE
(0010)," &
15-20
: linkage bit;
: linkage bit_vector(1 to 3));
Q08, R09, S09, Q09, Q10, Q11, Q12, S14, R14, Q13,"&
S15, R15, Q14, R16, Q15, R17, Q16, P15, Q17, P16,"&
M15, N15),"&
M01, L17, L01, K17, K01, J01, H17, H01, G17, G01," &
F01, E17, A13, A11, A10, A08, A07, A06, A05), " &
M02, L16, L02, K16, K02, J16, J02, H16, H02, G16," &
G02, F02, E16, B13, B11, B10, B08, B07, B05)," &
of
TDI
: signal is true;
of
TMS
: signal is true;
of
TDO
: signal is true;
TRSTBAR
: signal is true;
TCK
: signal is (33.0e6, BOTH);
(Sheet 2 of 4)
-- Define PinOut of PGA

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