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INTERRUPTS
In the event that both hardware and software requested interrupts are posted at the same level, the
hardware interrupt is delivered first while the software interrupt is left pending. As a result, if both
priority-31 hardware- and software-requested interrupts are pending, control is first transferred to
the interrupt handler for the hardware-requested interrupt. However, before the first instruction of
that handler can be executed, the pending software-requested interrupt is delivered, which causes
control to be transferred to the corresponding interrupt handler.
/* Model used to resolve interrupts between execution of all instructions */
if (NMI_pending && !block_NMI)
{ block_NMI = true;
vecnum = 248; vector_addr = 0;
PC.priority = 31;
push_local_register_set();
goto common_interrupt_process; }
if (ICON.gie == enabled) {
expand_HW_int();
temp = max(HW_Int_Priority, SW_Int_Priority);
if (temp == 31 || temp > PC.priority)
{ PC.priority = temp;
if (SW_Int_Priority > HW_Int_Priority) goto Deliver_SW_Int;
else{ vecnum = HW_vecnum; goto Deliver_HW_Int;}
}
}
11.6.7
Sampling Pending Interrupts in the Interrupt Table
At specific points, the processor checks the interrupt table for pending interrupts. If one is found, it
is handled as if the interrupt occurred at that time. In the i960 Jx processor, a check for pending
interrupts in the interrupt table is made when requesting a software interrupt with
servicing a software interrupt.
When a check of the interrupt table is made, the algorithm shown in
pending interrupts may be cached, the check for pending interrupt operation may not involve any
memory operations. The algorithm uses synchronization because there may be multiple agents posting
and unposting interrupts. In the algorithm, w, x, y, and z are temporary registers within the processor.
11-12
Example 11-3. Interrupt Resolution
/* Reset on return from NMI INTR handler */
, or when
sysctl
Example 11-4
is used. Since the
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