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INTERRUPTS
11.9.4
Maximum Interrupt Latency
In real-time applications, worst-case interrupt latency must be considered for critical handling of
external events. For example, an interrupt from a mechanical subsystem may need service to
calculate servo loop parameters to maintain directional control. Determining worst-case latency
depends on knowledge of the processor's instruction mix and operating environment as well as the
interrupt controller configuration. Excluding certain very long, uninterruptable instructions from
critical sections of code reduces worst-case interrupt latency to levels approaching the base latency.
The following tables present worst-case interrupt latencies based on possible execution of
destination),
(r3 destination),
divo
assumptions for these tables are the same as for
also assumed that the instructions are already in the cache and that tracing is disabled.
Table 11-4. Worst-Case Interrupt Latency Controlled by divo to Destination r15
Detection
Interrupt Type
NMI
Debounced
Dedicated Mode
XINT[7:0], TINT[1:0]
Debounced
Expanded Mode
Debounced
XINT[7:0], TINT[1:0]
NOTES:
a = MAX (0,N - 11)
b = MAX (0,N - 5)
c = MAX (0, N-4.7)
where "N" is the number of bus cycles needed to perform a word load.
11-38
or
instructions or software interrupt detection. The
calls
flushreg
Table
Vector
80960JA/JF
Caching
Option
Enabled
(Bus Clocks)
Fast
Yes
Yes
Yes
Fast
No
Yes
No
Yes
No
11-8, except for instruction execution. It is
Worst
Worst
80960JD
Latency
Latency
(Bus Clocks)
42
23.5
46
26
45
23.5
45+a
23.5+b
49
27.5
51+a
27.5+b
50
27.5
51+a
27.5+b
divo
(r15
Worst
80960JT (3x)
Latency
(Bus Clocks)
16.7
20.3
17
17+c
22.3
22.3+c
21
21+c
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