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8.10.3
OPERATION Faults ............................................................................................... 8-24
8.10.4
OVERRIDE Faults ................................................................................................. 8-26
8.10.5
PARALLEL Faults .................................................................................................. 8-27
8.10.6
PROTECTION Faults ............................................................................................ 8-28
8.10.7
TRACE Faults ........................................................................................................ 8-29
8.10.8
TYPE Faults .......................................................................................................... 8-32
CHAPTER 9
TRACING AND DEBUGGING
9.1
TRACE CONTROLS ..................................................................................................... 9-1
9.1.1
Trace Controls (TC) Register ................................................................................... 9-2
9.1.2
PC Trace Enable Bit and Trace-Fault-Pending Flag ............................................... 9-3
9.2
TRACE MODES ............................................................................................................ 9-3
9.2.1
Instruction Trace ...................................................................................................... 9-3
9.2.2
Branch Trace ........................................................................................................... 9-4
9.2.3
Call Trace ................................................................................................................ 9-4
9.2.4
Return Trace ............................................................................................................ 9-4
9.2.5
Prereturn Trace ....................................................................................................... 9-4
9.2.6
Supervisor Trace ..................................................................................................... 9-5
9.2.7
Mark Trace .............................................................................................................. 9-5
9.2.7.1
Software Breakpoints ....................................................................................... 9-5
9.2.7.2
Hardware Breakpoints ...................................................................................... 9-5
9.2.7.3
Requesting Modification Rights to Hardware Breakpoint Resources ............... 9-6
9.2.7.4
Breakpoint Control Register ............................................................................. 9-7
9.2.7.5
Data Address Breakpoint (DAB) Registers ....................................................... 9-9
9.2.7.6
Instruction Breakpoint (IPB) Registers ........................................................... 9-10
9.3
GENERATING A TRACE FAULT................................................................................ 9-11
9.4
HANDLING MULTIPLE TRACE EVENTS................................................................... 9-11
9.5
TRACE FAULT HANDLING PROCEDURE ................................................................ 9-12
9.5.1
Tracing and Interrupt Procedures .......................................................................... 9-12
9.5.2
Tracing on Calls and Returns ................................................................................ 9-12
9.5.2.1
Tracing on Explicit Call ................................................................................... 9-13
9.5.2.2
Tracing on Implicit Call ................................................................................... 9-14
9.5.2.3
Tracing on Return from Explicit Call ............................................................... 9-15
9.5.2.4
Tracing on Return from Implicit Call: Fault Case ............................................ 9-15
9.5.2.5
Tracing on Return from Implicit Call: Interrupt Case ...................................... 9-16
CHAPTER 10
TIMERS
10.1
TIMER REGISTERS.................................................................................................... 10-2
10.1.1
Timer Mode Registers (TMR0, TMR1) .................................................................. 10-3
10.1.1.1
Bit 0 - Terminal Count Status Bit (TMRx.tc) ................................................... 10-4
10.1.1.2
Bit 1 - Timer Enable (TMRx.enable) ............................................................... 10-4
10.1.1.3
Bit 2 - Timer Auto Reload Enable (TMRx.reload) ........................................... 10-5
10.1.1.4
Bit 3 - Timer Register Supervisor Read/Write Control (TMRx.sup) ................ 10-5
x
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