Instruction Operands - Intel i960 Jx Developer's Manual

31
OPCODE
31
OPCODE
31
OPCODE
31
OPCODE
31
OPCODE
Figure 5-1. Machine-Level Instruction Formats
5.1.3

Instruction Operands

This section identifies and describes operands that can be used with the instruction formats.
Format Operand(s)
REG src1, src2, src/dst
CTRL displacement
COBR src1, src2, displacement
MEM src/dst, efa
OPCODE
src/dst src2
src1
src2
displacement
Address
src/dst
Base
Address
src/dst
Scale
Base
32-Bit displacement
Description
src1 and src2 can be global registers, local registers or
literals. src/dst is either a global or a local register.
CTRL format is used for branch and call instructions.
displacement value indicates the target instruction of the
branch or call.
src1, src2 indicate values to be compared; displacement
indicates branch target. src1 can specify a global register, local
register or a literal. src2 can specify a global or local register.
Specifies source or destination register and an effective address
(efa) formed by using the processor's addressing modes as
described in section 2.3, "MEMORY ADDRESSING
MODES" (pg. 2-6). Registers specified in a MEM format
instruction must be either a global or local register.
INSTRUCTION SET OVERVIEW
0
src1
REG
0
COBR
displacement
0
CTRL
0
Offset
MEMA
0
Index MEMB
5
5-3