Microcoded Instructions; Multiply-Divide Unit Instructions; Multi-Cycle Register Operations - Intel i960 Jx Developer's Manual

5.3.1.3

Microcoded Instructions

While the majority of instructions on the i960 Jx processor are single cycle and are executed
directly by processor hardware, some require microcode emulation. Entry into a microcode routine
requires two cycles. Exit from microcode typically requires two cycles. For some routines, one
cycle of the exit process can execute in parallel with another instruction, thus saving one cycle of
execution time.
5.3.1.4

Multiply-Divide Unit Instructions

The Multiply-Divide Unit (MDU) of the i960 Jx processor performs a number of multi-cycle
arithmetic operations. These can range from 2 cycles for a 16-bitx32-bit
32-bitx32-bit , to 30+ cycles for an
mulo
Once issued, these MDU instructions are executed in parallel with other non-MDU instructions
that do not depend on the result of the MDU operation. Attempting to issue another MDU
instruction while a current MDU instruction is executing, stalls the processor until the first one
completes.
5.3.1.5

Multi-Cycle Register Operations

A few register operations can also take multiple cycles. The following instructions are all
performed in microcode:
• bswap • extract
• movq • shrdi
• testl • testle
On the i960 Jx processor, test<cc>
0,1,dst , which is executed in one cycle directly by processor hardware.
Multi-register move operation execution time can be decreased at the expense of cache utilization
and code density by using
mov
instructions.
.
ediv
• eshro • modify
• scanbit • spanbit
• teste • testne
dst is microcoded and takes many more cycles than
the appropriate number of times instead of
INSTRUCTION SET OVERVIEW
, 4 cycles for a
mulo
• movl • movt
• testno • testo
• testg • testge
, and
movl movt
5
SEL<cc>
movq
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