Table 11-8. Worst-Case Interrupt Latency Controlled By Flushreg Of One Stack Frame - Intel i960 Jx Developer's Manual

Table 11-8. Worst-Case Interrupt Latency Controlled by flushreg of One Stack Frame

Detection
Interrupt Type
Option
NMI
Debounced
Dedicated Mode
XINT[7:0], TINT[1:0]
Debounced
Expanded Mode
Debounced
XINT[7:0], TINT[1:0]
Notes:
a = MAX (0, M - 15)
b = MAX (0, M - 28)
c = MAX (0, N - 7)
d = MAX (0, M - 7.5)
e = MAX (0, M - 15)
f = MAX (0, n - 3.5)
stq_cycles = number of cycles to execute stq instruction.
g, h, i account for scoreboarding due to the possibility of long memory access latencies.
j and k account for long STQ time affecting the loading of the interrupt vector from the Interrupt Table.
where "M" is the number of bus cycles needed to perform a quad word store and "N" is the number of bus
cycles needed to perform a word load. Interrupt latency increases rapidly as the number of flushed stack
frames increases.
Vector
80960JA/JF
Caching
Enabled
(Bus Clocks)
Fast Yes
Yes
Yes
Fast
No 89+a+b+c
Yes
No 93+a+b+c
Yes
No 93+a+b+c
A = g+h+i
g = MAX (0,M - 4.7)
h = MAX (0,2M - [7.3+g])
i = MAX (0,3M - [13.7+g+h])
j = MAX (0,4M+h - 53)
k = MAX (0,N - [7-j])
INTERRUPTS
Worst Worst
80960JD
Latency Latency
(Bus Clocks)
77+a+b 41+d+e
81+a+b 43+d+e
82+a+b 43+d+e
47.5+d+e+f
86+a+b 47+d+e
51+d+e+f
88+a+b 47.5+d+e
52+d+e+f
Worst
80960JT (1x)
Latency
(Bus Clocks)
28.3+A
32.3+A
30+A
32+A+k
34+A
35.3+A+k
34+A
37+A+k
11
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