Figure 14.1. Bus States With Arbitration - Intel i960 Jx Developer's Manual

Microprocessor
Table of Contents

Advertisement

T
a
REQUEST PENDING
AND (NO HOLD OR
LOCKED)
NO REQUEST
AND (NO HOLD
OR LOCKED)
T
i
ONCE & RESET
DEASSERTION
T
RESET
o
T
— IDLE STATE
I
T
— ADDRESS STATE
A
T
/T
— WAIT/DATA STATE
W
D
T
— RECOVERY STATE
R
T
— HOLD STATE
H
T
— ONCE STATE
O

Figure 14.1. Bus States with Arbitration

(READY AND BURST)
T
/T
w
RECOVERED
AND REQUEST
PENDING AND
(NO HOLD OR
LOCKED)
RECOVERED AND
REQUEST
NO REQUEST AND
PENDING
AND NO HOLD
NO REQUEST
T
AND NO HOLD
h
HOLD AND
NOT LOCKED
HOLD
READY — RDYRCV ASSERTED
NOT READY — RDYRCV NOT ASSERTED
BURST — BLAST NOT ASSERTED
NO BURST — BLAST ASSERTED
RECOVERED — RDYRCV NOT ASSERTED
NOT RECOVERED — RDYRCV ASSERTED
REQUEST PENDING — NEW TRANSACTION
NO REQUEST — NO NEW TRANSACTION
HOLD — HOLD REQUEST ASSERTED
NO HOLD — HOLD REQUEST NOT ASSERTED
LOCKED — ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS
NOT LOCKED — NO ATOMIC EXECUTION IN PROGRESS
RESET — RESET ASSERTED
ONCE — ONCE ASSERTED
EXTERNAL BUS
OR NOT READY
d
READY AND
NO BURST
T
r
(NO HOLD OR
LOCKED)
RECOVERED AND
HOLD AND NOT
LOCKED
NOT
RECOVERED
14
14-3

Advertisement

Table of Contents
loading

Table of Contents