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Each logical memory template is defined by programming Logical Memory Configuration
(LMCON) registers. An LMCON Register pair defines a data template for areas of memory that
have common logical attributes. The Jx microprocessor has two pairs of LMCON registers —
defining two separate templates. The extent of each data template is described by an address (on 4
Kbyte boundaries) and an address mask. The address is programmed in the Logical Memory
Address register (LMADR). The mask is programmed in the Logical Memory Mask register
(LMMSK). These two registers constitute the LMCON register pair.
The Default Logical Memory Configuration register is used to provide configuration data for areas
of memory that do not fall within one of the two logical data templates. The DLMCON also
specifies byte-ordering (little endian/big endian) for all data accesses in memory, including
on-chip data RAM.
The LMCON registers and their programming are described in
Logical Memory
Attributes.
13.2
Differences With Previous i960 Processors
The mechanism described in this chapter is not implemented on the i960 Kx or Sx processors.
Although the i960 Cx processor has a memory configuration mechanism, it is different from the
80960Jx's in the following ways:
•
For the purposes of assigning physical and logical memory attributes, the i960 Cx processor
evenly divides physical memory into 16 contiguous regions. When assigning physical
memory attributes, the Jx divides memory into 8 contiguous, 512 Mbyte regions starting on
512 Mbyte boundaries. The logical memory templates of the i960 Jx processor provide a
programmable association of logical memory addresses, whereas the i960 Cx processor
assigns these attributes to the physical memory regions.
•
The i960 Cx processor provides per-region programming of wait states, address pipelining and
bursting. No such mechanisms exist on the 80960Jx. Bus wait states must be generated using
external logic.
MEMORY CONFIGURATION
Section 13.6, Programming the
13
13-3
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