Timer State Diagram; Figure 10-5. Timer Unit State Diagram - Intel i960 Jx Developer's Manual

10.6

TIMER STATE DIAGRAM

Figure 10-5 shows the common states of the Timer Unit. For uncommon conditions see
section 10.5, "UNCOMMON TCRX AND TRRX CONDITIONS" (pg.
SW Write
(TMRx.enable = 0)
TMRx.enable = 1
TMRx.enable = 0
Hardware/Software Reset
TMRx.enable = 0
TMRx.reload = 0
TMRx.sup = 0
TMRx.csel1:0 = 0
IPND.tip = 0
Bus Clock or
IDLE
SW Read
SW Write (TMRx.enable = 1)
TMRx.enable = 1
TMRx.reload =user value
TMRx.sup = user value
TMRx.csel1:0 = user value
TCRx = 0
Initial TCRx
Check
TCRx != 0
SW Read
Decrement
TCRx
SW Write
TMRx.reload =user value
TMRx.sup = user value
TMRx.csel1:0 = user value
SW Write
SW Read/Write & Reload = 0
SW Read
TC = 0

Figure 10-5. Timer Unit State Diagram

TIMERS
10-12).
See section 10.5, "UNCOMMON
TCRX AND TRRX CONDITIONS"
(pg. 10-12)
Clock Unit Tick
and TCRx != 0
TCRx = 0
TC = 0
TC = 1
IPND.tip = 1
TMRx.enable = 1
TMRx.enable = 0
TCRx = TRRx
Reload = 1
TC Detected
State
Bus Clock
10
10-13