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10.1.1.5
Bits 4, 5 - Timer Input Clock Select (TMRx.csel1:0) ....................................... 10-6
10.1.2
Timer Count Register (TCR0, TCR1) .................................................................... 10-6
10.1.3
Timer Reload Register (TRR0, TRR1) .................................................................. 10-7
10.2
TIMER OPERATION ................................................................................................... 10-7
10.2.1
Basic Timer Operation ........................................................................................... 10-7
10.2.2
Load/Store Access Latency for Timer Registers ................................................... 10-9
10.3
TIMER INTERRUPTS ............................................................................................... 10-11
10.4
POWERUP/RESET INITIALIZATION ....................................................................... 10-11
10.5
UNCOMMON TCRX AND TRRX CONDITIONS....................................................... 10-12
10.6
TIMER STATE DIAGRAM......................................................................................... 10-13
CHAPTER 11
INTERRUPTS
11.1
OVERVIEW ................................................................................................................. 11-1
®
11.1.1
The i960
Jx Processor Interrupt Controller .......................................................... 11-2
11.2
SOFTWARE REQUIREMENTS FOR INTERRUPT HANDLING ................................ 11-3
11.3
INTERRUPT PRIORITY.............................................................................................. 11-3
11.4
INTERRUPT TABLE ................................................................................................... 11-4
11.4.1
Vector Entries ........................................................................................................ 11-5
11.4.2
Pending Interrupts ................................................................................................. 11-5
11.4.3
Caching Portions of the Interrupt Table ................................................................. 11-6
11.5
INTERRUPT STACK AND INTERRUPT RECORD .................................................... 11-7
11.6
MANAGING INTERRUPT REQUESTS ...................................................................... 11-8
11.6.1
External Interrupts ................................................................................................. 11-8
11.6.2
Non-Maskable Interrupt (NMI) ............................................................................... 11-8
11.6.3
Timer Interrupts ..................................................................................................... 11-9
11.6.4
Software Interrupts ................................................................................................ 11-9
11.6.5
Posting Interrupts .................................................................................................. 11-9
11.6.5.1
Posting Software Interrupts via sysctl ............................................................ 11-9
11.6.5.2
Posting Software Interrupts Directly in the Interrupt Table ........................... 11-11
11.6.5.3
Posting External Interrupts ........................................................................... 11-11
11.6.5.4
Posting Hardware Interrupts ........................................................................ 11-11
11.6.6
Resolving Interrupt Priority .................................................................................. 11-11
11.6.7
Sampling Pending Interrupts in the Interrupt Table ............................................. 11-12
11.6.8
Interrupt Controller Modes ................................................................................... 11-14
11.6.8.1
Dedicated Mode ........................................................................................... 11-14
11.6.8.2
Expanded Mode ........................................................................................... 11-15
11.6.8.3
Mixed Mode .................................................................................................. 11-17
11.6.9
Saving the Interrupt Mask ................................................................................... 11-17
11.7
EXTERNAL INTERFACE DESCRIPTION ................................................................ 11-18
11.7.1
Pin Descriptions .................................................................................................. 11-18
11.7.2
Interrupt Detection Options ................................................................................. 11-19
11.7.3
Memory-Mapped Control Registers ..................................................................... 11-21
11.7.4
Interrupt Control Register (ICON) ........................................................................ 11-22
xi
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