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A.5.2
Implementation-Specific Instructions
Most of the processor's instruction set is defined by the core architecture. Several instructions are
specific to the i960 Jx processor. These instructions are either functional extensions to the
instruction set or instructions that control implementation-specific functions.
INSTRUCTION SET REFERENCE
•
dcctl
Data cache control
•
icctl
Instruction cache control
Interrupt control
•
intctl
•
halt
Halt CPU
Application code using implementation-specific instructions is not directly portable to the entire
i960 processor family. Attempted execution of an unimplemented instruction results in an
OPERATION.INVALID_OPCODE fault.
The i960 Jx and Hx processors introduce several new core instructions. These instructions may or
may not be supported on other i960 processors. The new core instructions include:
•
ADD<cc>
Conditional add
Byte swap
•
bswap
•
COMPARE
Byte and short compares
A.6
EXTENDED REGISTER SET
The i960 architecture defines a way to address an extended set of 32 registers in addition to the
16 global and 16 local registers. Some or all of these registers may be implemented on a specific
i960 processor. There are no extended registers implemented on the i960 Jx processors.
A.7
INITIALIZATION
The i960 architecture does not define an initialization mechanism. The way that an i960-based
product is initialized is implementation dependent. Code that accesses locations in initialization
data structures is not portable to other i960 processor implementations.
The i960 Jx processors use an initialization boot record (IBR) and a process control block (PRCB)
to hold initial configuration and a first instruction pointer.
CONSIDERATIONS FOR WRITING PORTABLE CODE
denotes each implementation-specific instruction.
•
inten
Global interrupt enable
•
intdis
Global interrupt disable
System control
•
sysctl
•
eshro
•
SEL<cc>
•
SUB<cc>
CHAPTER 6,
Extended shift right ordinal
Conditional select
Conditional subtract
A-5
A
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