A.2 Address Space Restrictions; A.2.1 Reserved Memory; A.2.2 Initialization Boot Record; A.2.3 Internal Data Ram - Intel i960 Jx Developer's Manual

Microprocessor
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CONSIDERATIONS FOR WRITING PORTABLE CODE
A.2
ADDRESS SPACE RESTRICTIONS
Address space properties that are implementation-specific to this microprocessor are described in
the subsections that follow.
A.2.1
Reserved Memory
Addresses in the range FF00 0000H to FFFF FFFFH are reserved by the i960 architecture. The
i960 Jx processor cannot access this memory, so any use of reserved memory by other i960
processor code is not portable to the i960 Jx processor.
A.2.2
Initialization Boot Record
The i960 Jx processor uses a section just below the reserved address space for the initialization
boot record; see
section 12.3.1.1, "Initialization Boot Record (IBR)" (pg.
the i960 Cx processor, which requires that user to place the Initialization Boot Record (IBR) in a
section of reserved memory.
The initialization boot record may not exist or may be structured differently for other
implementations of the i960 architecture.
A.2.3
Internal Data RAM
Internal data RAM — an i960 Jx processor implementation-specific feature — is mapped to the first
1 Kbytes of the processor's address space (0000H – 03FFH). The on-chip data RAM may be used to
cache interrupt vectors and may be protected against user and supervisor mode writes. Code that
relies on these special features is not directly portable to all i960 processor implementations.
A.2.4
Instruction Cache
The i960 architecture allows instructions to be cached on-chip in a non-transparent fashion. This
means that the cache may not detect modification of the program memory by loads, stores or
alteration by external agents. Each implementation of the i960 architecture that uses an integrated
instruction cache provides a mechanism to purge the cache or some other method that forces
consistency between external memory and internal cache.
This feature is implementation dependent. Application code that supports modification of the code
space must use this implementation-specific feature and, therefore, is not object-code portable to
all i960 processor implementations.
A-2
12-13). This differs from

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