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3.7.4
Trace Controls (TC) Register
The TC register, in conjunction with the PC register, controls processor tracing facilities. It contains trace
mode enable bits and trace event flags that are used to enable specific tracing modes and record trace
events, respectively. Trace controls are described in
3.8
USER-SUPERVISOR PROTECTION MODEL
The processor can be in either of two execution modes: user or supervisor. The capability of a
separate user and supervisor execution mode creates a code and data protection mechanism
referred to as the user-supervisor protection model. This mechanism allows code, data and stack
for a kernel (or system executive) to reside in the same address space as code, data and stack for the
application. The mechanism restricts access to all or parts of the kernel by the application code.
This protection mechanism prevents application software from inadvertently altering the kernel.
3.8.1
Supervisor Mode Resources
Supervisor mode is a privileged mode that provides several additional capabilities over user mode.
•
When the processor switches to supervisor mode, it also switches to the supervisor stack.
Switching to the supervisor stack helps maintain a kernel's integrity. For example, it allows
access to system debugging software or a system monitor, even when an application's program
destroys its own stack.
•
In supervisor mode, the processor is allowed access to a set of supervisor-only functions and
instructions. For example, the processor uses supervisor mode to handle interrupts and trace
faults. Operations that can modify interrupt controller behavior or reconfigure bus controller
characteristics can be performed only in supervisor mode. These functions include modification
of control registers and internal data RAM that is dedicated to interrupt controllers. A fault is
generated when supervisor-only operations are attempted while the processor is in user mode.
The PC register execution mode flag specifies processor execution mode. The processor automati-
cally sets and clears this flag when it switches between the two execution modes.
•
dcctl
(data cache control)
•
icctl
(instruction cache control)
•
(global interrupt enable and disable)
intctl
•
intdis
(global interrupt disable)
•
halt
(halt CPU)
Note that all of these instructions return a TYPE.MISMATCH fault when executed in user mode.
PROGRAMMING ENVIRONMENT
CHAPTER 9, TRACING AND
•
inten
(global interrupt enable)
•
modpc
(modify process controls w/
non-zero mask)
•
(system control)
sysctl
•
Protected internal data RAM or Supervisor
MMR space write
•
Protected timer unit registers
DEBUGGING.
3
3-23
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