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Intel Core i7 Extreme Edition Datasheet

Intel Core i7 Extreme Edition Datasheet

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®
Intel
Core™ i7 Processor Extreme
®
Edition and Intel
Core™ i7
Processor
Datasheet, Volume 1
November 2008
Document # 320834-001

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Summary of Contents for Intel Core i7 Extreme Edition

  • Page 1 ® Intel Core™ i7 Processor Extreme ® Edition and Intel Core™ i7 Processor Datasheet, Volume 1 November 2008 Document # 320834-001...
  • Page 2 The Intel Core™ i7 processor Extreme Edition and Intel Core™ i7 processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

  • Page 3: Table Of Contents

    Contents Introduction ......................9 Terminology ..................... 10 References ....................... 11 Electrical Specifications ................... 13 Intel® QPI Differential Signaling ................. 13 Power and Ground Lands..................13 Decoupling Guidelines ..................13 2.3.1 VCC, VTTA, VTTD, VDDQ Decoupling............14 Processor Clocking (BCLK_DP, BCLK_DN) ............. 14 2.4.1...
  • Page 4 Clock Control and Low Power States ..............89 7.2.1 Thread and Core Power State Descriptions ..........90 7.2.2 Package Power State Descriptions .............91 Sleep States .....................92 ® ACPI P-States (Intel Turbo Boost Technology) .............92 ® Enhanced Intel SpeedStep Technology ...............93 Boxed Processor Specifications................95 Introduction ......................95 Mechanical Specifications ..................96...
  • Page 5 Tables References ....................... 11 Voltage Identification Definition................15 Market Segment Selection Truth Table for MS_ID[2:0] ........... 17 Signal Groups ....................18 Signals with ODT....................19 PECI DC Electrical Limits ..................20 Processor Absolute Minimum and Maximum Ratings ..........22 Voltage and Current Specifications............... 23 VCC Static and Transient Tolerance ..............
  • Page 6 Datasheet...
  • Page 7 ® ® Intel Core™ i7 Processor Extreme Edition and Intel Core™ i7 Processor Features • Available at 3.20 GHz, 2.93 GHz, and • Multiple low-power states 2.66 GHz • 8-way cache associativity provides improved ® • Enhanced Intel Speedstep Technology cache hit rate on load/store operations ®...

  • Page 8: Revision History

    Revision History Revision Description Date Number -001 • Initial release November 2008 § Datasheet...

  • Page 9: Introduction

    Core™ i7 processor will be referred to as “the processor.” Note: The Intel Core™ i7 processor refers to the Intel Core™ i7 processors i7-940 and i7-920. Note: The Intel Core™ i7 processor Extreme Edition refers to the Intel Core™ i7 processor Extreme Edition i7-965.

  • Page 10: Terminology

    — The entire product, including processor substrate and integrated heat spreader (IHS). • 1366-land LGA package — The Intel Core™ i7 processor Extreme Edition and Intel Core™ i7 processor is available in a Flip-Chip Land Grid Array (FC-LGA) package, consisting of the processor mounted on a land grid array substrate with an integrated heat spreader (IHS).

  • Page 11: References

    ® • Intel Virtualization Technology (Intel VT) — A set of hardware enhancements to Intel server and client platforms that can improve virtualization ® solutions. Intel VT provides a foundation for widely-deployed virtualization solutions and enables a more robust hardware assisted virtualization solution. More information can be found at: http://www.intel.com/technology/virtualization/...
  • Page 12 Introduction Datasheet...

  • Page 13: Electrical Specifications

    Intel QPI Differential Signaling The processor provides an Intel QPI port for high speed serial transfer between other Intel QPI-enabled components. The Intel QPI port consists of two unidirectional links (for transmit and receive). Intel QPI uses a differential signalling scheme where pairs of opposite-polarity (D_P, D_N) signals are used.

  • Page 14: Vcc, Vtta, Vttd, Vddq Decoupling

    The processor core, Intel QPI, and integrated memory controller frequencies are generated from BCLK_DP and BCLK_DN. Unlike previous processors based on front side bus architecture, there is no direct link between core frequency and Intel QPI link frequency (such as, no core frequency to Intel QPI multiplier). The processor maximum core frequency, Intel QPI link frequency and integrated memory controller frequency, are set during manufacturing.

  • Page 15: Voltage Identification Definition

    Electrical Specifications The processor uses eight voltage identification signals, VID[7:0], to support automatic selection of voltages. Table 2-1 specifies the voltage level corresponding to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level.
  • Page 16 Electrical Specifications Table 2-1. Voltage Identification Definition (Sheet 2 of 3) CC_MAX CC_MAX 1.41875 0.85000 1.41250 0.84374 1.40625 0.83750 1.40000 0.83125 1.39375 0.82500 1.38750 0.81875 1.38125 0.81250 1.37500 0.80625 1.36875 0.80000 1.36250 0.79375 1.35625 0.78750 1.35000 0.78125 1.34375 0.77500 1.33750 0.76875 1.33125 0.76250...

  • Page 17: Reserved Or Unused Signals

    Reserved Reserved Reserved Reserved Intel Core™ i7 processor Extreme Edition and Intel Core™ i7 processor Reserved 1. The MSID[2:0] signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying.

  • Page 18: Signal Groups

    Signal Group Type Signals System Reference Clock Differential Clock Input BCLK_DP, BCLK_DN ® Intel QPI Signal Groups Differential Intel QPI Input QPI_DRX_D[N/P][19:0], QPI_CLKRX_DP, QPI_CLKRX_DN Differential Intel QPI Output QPI_DTX_D[N/P][19:0], QPI_CLKTX_DP, QPI_CLKTX_DN DDR3 Reference Clocks DDR3 Output DDR{0/1/2}_CLK[D/P][3:0] Differential DDR3 Command Signals...

  • Page 19: Test Access Port (Tap) Connection

    Electrical Specifications Table 2-3. Signal Groups (Sheet 2 of 2) Signal Group Type Signals Single ended CMOS Output VTT_VID[4:2] Single ended Analog Input ISENSE Reset Signal Single ended Reset Input RESET# PWRGOOD Signals Single ended Asynchronous Input VCCPWRGOOD, VTTPWRGOOD, VDDPWRGOOD Power/Other Power VCC, VTTA, VTTD, VCCPLL, VDDQ...

  • Page 20: Platform Environmental Control Interface (Peci) Dc Specifications

    Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.

  • Page 21: Input Device Hysteresis

    Electrical Specifications 2.9.2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-2 as a guide for input buffer design. Figure 2-2. Input Device Hysteresis Maximum V PECI High Range Minimum V...

  • Page 22: Processor Dc Specifications

    Electrical Specifications Table 2-6. Processor Absolute Minimum and Maximum Ratings 1, 2 Symbol Parameter Unit Notes Processor Core voltage with respect to V -0.3 1.55 Voltage for the analog portion of the integrated — 1.35 memory controller, QPI link and Shared Cache with respect to V Voltage for the digital portion of the integrated —...

  • Page 23: Dc Voltage And Current Specification

    VID employed by the processor during a power management event (Adaptive ® Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States). The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ...
  • Page 24 Electrical Specifications Table 2-8. Static and Transient Tolerance Notes CC_Max CC_Typ CC_Min VID - 0.000 VID - 0.019 VID - 0.038 1, 2, 3 VID - 0.004 VID - 0.023 VID - 0.042 1, 2, 3 VID - 0.008 VID - 0.027 VID - 0.046 1, 2, 3 VID - 0.012...

  • Page 25: Vcc Static And Transient Tolerance Load Lines

    Electrical Specifications Figure 2-3. Static and Transient Tolerance Load Lines Icc [A] VID - 0.000 VID - 0.013 VID - 0.025 Vcc Maximum VID - 0.038 VID - 0.050 VID - 0.063 VID - 0.075 Vcc Typical VID - 0.088 VID - 0.100 VID - 0.113 Vcc Minimum...
  • Page 26 Electrical Specifications Table 2-10. V Static and Transient Tolerance Notes TT_Max TT_Typ TT_Min VID + 0.0315 VID – 0.0000 VID – 0.0315 VID + 0.0255 VID – 0.0060 VID – 0.0375 VID + 0.0195 VID – 0.0120 VID – 0.0435 VID + 0.0135 VID –...

  • Page 27: Vtt Static And Transient Tolerance Load Line

    Electrical Specifications Figure 2-4. Static and Transient Tolerance Load Line Itt [A] (sum of Itta and Ittd) 0.0500 0.0375 0.0250 0.0125 0.0000 -0.0125 Vtt Maximum -0.0250 -0.0375 -0.0500 -0.0625 -0.0750 Vtt Typical -0.0875 -0.1000 -0.1125 -0.1250 Vtt Minimum -0.1375 -0.1500 -0.1625 -0.1750 -0.1875...

  • Page 28: Reset# Signal Dc Specifications

    Electrical Specifications and V may experience excursions above V . However, input signal drivers must comply with the signal quality specifications. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design guide for implementation details. DDR_COMP[2:0] resistors are to V Table 2-12.

  • Page 29: Vcc Overshoot Specification

    Electrical Specifications Table 2-15. Control Sideband Signal Group DC Specifications Symbol Parameter Units Notes Input Low Voltage — — 0.64 Input High Voltage 0.76 — — Output Low Voltage / (R — — sys_term Output High Voltage — — Buffer on Resistance —...

  • Page 30: Die Voltage Validation

    Electrical Specifications Figure 2-5. Overshoot Example Waveform Example Overshoot Waveform VID + V Time : Overshoot time above VID : Overshoot above VID 2.11.3 Die Voltage Validation Core voltage (V ) overshoot events at the processor must meet the specifications in Table 2-16 when measured across the VCC_SENSE and VSS_SENSE lands.

  • Page 31: Package Mechanical Specifications

    Package Mechanical Specifications Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array package that interfaces with the motherboard via an LGA1366 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor thermal solutions, such as a heatsink.

  • Page 32: Processor Package Drawing (Sheet 1 Of 2)

    Package Mechanical Specifications Figure 3-2. Processor Package Drawing (Sheet 1 of 2) Datasheet...

  • Page 33: Processor Package Drawing (Sheet 2 Of 2)

    Package Mechanical Specifications Figure 3-3. Processor Package Drawing (Sheet 2 of 2) Datasheet...

  • Page 34: Processor Component Keep-Out Zones

    Package Mechanical Specifications Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep- out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate.

  • Page 35: Processor Mass Specification

    Substrate Lands Gold Plated Copper Processor Markings Figure 3-4 shows the topside markings on the processor. This diagram is to aid in the identification of the processor. Figure 3-4. Processor Top-Side Markings INTEL ©'07 PROC# BRAND SLxxx [COO] SPEED/CACHE/INTC/FMB [FPO] Datasheet...

  • Page 36: Processor Land Coordinates

    Package Mechanical Specifications Processor Land Coordinates Figure 3-5 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Figure 3-5. Processor Land Coordinates and Quadrants (Bottom View) § Datasheet...

  • Page 37: Land Listing

    Land Listing Land Listing This section provides sorted land list in Table 4-1 Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by land number. Table 4-1.
  • Page 38 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 3 of 36) (Sheet 4 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type DDR0_DQ[3] CMOS DDR0_DQ[8] CMOS DDR0_DQ[30] CMOS DDR0_DQ[9]...
  • Page 39 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 5 of 36) (Sheet 6 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type DDR0_RESET# CMOS DDR1_DQ[24] CMOS DDR0_WE# CMOS DDR1_DQ[25]...
  • Page 40 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 7 of 36) (Sheet 8 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type DDR1_DQ[6] CMOS DDR1_MA[9] CMOS DDR1_DQ[60] CMOS DDR1_ODT[0]...
  • Page 41 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 9 of 36) (Sheet 10 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type DDR2_DQ[19] CMOS DDR2_DQ[54] CMOS DDR2_DQ[2] CMOS DDR2_DQ[55]...
  • Page 42 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 11 of 36) (Sheet 12 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type DDR2_MA[3] CMOS QPI_DRX_DN[3] AY36 DDR2_MA[4] CMOS QPI_DRX_DN[4]...
  • Page 43 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 13 of 36) (Sheet 14 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type QPI_DTX_DN[2] AK38 RSVD QPI_DTX_DN[3] AJ39 RSVD QPI_DTX_DN[4]...
  • Page 44 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 15 of 36) (Sheet 16 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type RSVD RSVD RSVD RSVD RSVD RSVD RSVD...
  • Page 45 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 17 of 36) (Sheet 18 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type RSVD RSVD AL41 RSVD RSVD RSVD RSVD...
  • Page 46 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 19 of 36) (Sheet 20 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type RSVD RSVD RSVD RSVD RSVD RSVD RSVD...
  • Page 47 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 21 of 36) (Sheet 22 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type AK33 AN25 AL12 AN27 AL13 AN28 AL15...
  • Page 48 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 23 of 36) (Sheet 24 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type AT12 AV19 AT13 AV21 AT15 AV24 AT16...
  • Page 49 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 25 of 36) (Sheet 26 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type AY28 VCCPLL AY30 VCCPWRGOOD Asynch AY31 VDDPWRGOOD...
  • Page 50 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 27 of 36) (Sheet 28 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type VDDQ AD37 VDDQ AD41 VDDQ AD43 VDDQ...
  • Page 51 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 29 of 36) (Sheet 30 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type AL11 AN35 AL14 AN37 AL17 AN41 AL20...
  • Page 52 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 31 of 36) (Sheet 32 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type AT23 AW20 AT26 AW22 AT29 AW23 AT32...
  • Page 53 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 33 of 36) (Sheet 34 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type Datasheet...
  • Page 54 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 35 of 36) (Sheet 36 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type VTTD AC11 VTTD AC33 VTTD AC34 VTTD...

  • Page 55: Land Listing By Land Number

    Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 2 of 36) (Sheet 1 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type AA39 DDR0_MA[13] CMOS BCLK_ITP_DN CMOS VDDQ AA40...
  • Page 56 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 3 of 36) (Sheet 4 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type AC37 CAT_ERR# RSVD AC38 QPI_DTX_DN[16] AE33 VTTA...
  • Page 57 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 5 of 36) (Sheet 6 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type VTTD AH43 QPI_DTX_DN[8] RSVD FC_AH5 AG10 RSVD...
  • Page 58 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 7 of 36) (Sheet 8 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type RSVD AL16 AK20 AL17 AK21 AL18 AK22...
  • Page 59 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 9 of 36) (Sheet 10 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type AM12 AM13 RSVD AM14 AN10 VID[4]/CSC[1] CMOS...
  • Page 60 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 11 of 36) (Sheet 12 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type RSVD AP40 QPI_DRX_DN[17] RSVD AP41 QPI_DRX_DP[17] AP42...
  • Page 61 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 13 of 36) (Sheet 14 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type AR37 RSVD AT33 AR38 QPI_DRX_DN[19] AT34 AR39...
  • Page 62 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 15 of 36) (Sheet 16 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type RSVD AV26 AU30 AV27 AU31 AV28 AU32...
  • Page 63 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 17 of 36) (Sheet 18 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type AW22 AY20 AW23 AY21 AW24 AY22 AW25...
  • Page 64 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 19 of 36) (Sheet 20 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type DDR0_MA[10] CMOS BA17 BA18 RSVD BA19 DDR0_MA[1]...
  • Page 65 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 21 of 36) (Sheet 22 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type DDR0_MA[6] CMOS RSVD VDDQ DDR1_CLK_N[0] CLOCK DDR0_MA[9]...
  • Page 66 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 23 of 36) (Sheet 24 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type DDR2_CS#[4] CMOS DDR2_ODT[1] CMOS DDR0_CLK_N[2] CLOCK VDDQ...
  • Page 67 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 25 of 36) (Sheet 26 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type DDR0_DQ[44] CMOS DDR1_DQS_N[5] CMOS DDR2_DQ[37] CMOS DDR2_DQ[36]...
  • Page 68 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 27 of 36) (Sheet 28 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type DDR0_DQ[16] CMOS RSVD DDR2_DQ[19] CMOS DDR0_DQ[17] CMOS...
  • Page 69 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 29 of 36) (Sheet 30 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type RSVD DDR1_DQS_P[3] CMOS DDR1_DQ[18] CMOS DDR1_DQS_N[3] CMOS...
  • Page 70 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 31 of 36) (Sheet 32 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type VDDQ RSVD DDR0_DQ[9] CMOS DDR0_DQ[52] CMOS DDR2_DQ[49]...
  • Page 71 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 33 of 36) (Sheet 34 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type DDR1_DQS_P[1] CMOS VCCPLL DDR2_DQ[10] CMOS DDR2_DQ[4] CMOS...
  • Page 72 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 35 of 36) (Sheet 36 of 36) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type DDR0_DQS_N[7] CMOS DDR1_DQ[59] CMOS DDR1_DQ[58] CMOS DDR0_DQS_P[7]...

  • Page 73: Signal Definitions

    COMP0 Impedance compensation must be terminated on the system board using a precision resistor. QPI_CLKRX_DN Intel QPI received clock is the input clock that corresponds to the received data. QPI_CLKRX_DP QPI_CLKTX_DN Intel QPI forwarded clock sent with the outbound data.
  • Page 74 Signal Definitions Table 5-1. Signal Definitions (Sheet 2 of 4) Name Type Description Notes DDR{0/1/2}_MA[15:0] Selects the Row address for Reads and writes, and the column address for activates. Also used to set values for DRAM configuration registers. DDR{0/1/2}_ODT[3:0] Enables various combinations of termination resistance in the target and non- target DIMMs when data is read or written DDR{0/1/2}_RAS# Row Address Strobe.
  • Page 75 Signal Definitions Table 5-1. Signal Definitions (Sheet 3 of 4) Name Type Description Notes THERMTRIP# Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor.
  • Page 76 Signal Definitions Table 5-1. Signal Definitions (Sheet 4 of 4) Name Type Description Notes VTT_VID[4:2] VTT_VID[2:4] (VTTVoltage ID) are used to support automatic selection of power supply voltages (V VTT_SENSE VTT_SENSE and VSS_SENSE_VTT provide an isolated, low impedance connection to the processor V voltage and ground.

  • Page 77: Thermal Specifications

    The fan speed control algorithm can be updated to utilize the additional information to optimize acoustics. To allow the optimal operation and long-term reliability of Intel processor-based systems, the processor thermal solution must deliver the specified thermal solution performance in response to the DTS sensor value.

  • Page 78: Processor Thermal Specifications

    39 °C. AMBIENT Processor idle power is specified under the lowest possible idle state: processor package C6 state. Achieving processor package C6 state is not supported by all chipsets. See Intel X58 Express Chipset specifications for more details. Datasheet...

  • Page 79: Processor Thermal Profile

    Thermal Specifications Figure 6-1. Processor Thermal Profile 70.0 y = 43.2 + 0.19 * P 65.0 60.0 55.0 50.0 45.0 40.0 TTV Power (W) Notes: Refer to Table 6-2 for discrete points that constitute the thermal profile. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for system and environmental implementation details.
  • Page 80 Thermal Specifications 6.1.1.1 Specification for Operation Where Digital Thermal Sensor Exceeds CONTROL When the DTS value is less than T the fan speed control algorithm can reduce CONTROL the speed of the thermal solution fan. This remains the same as with the previous guidance for fan speed control.

  • Page 81: Thermal Metrology

    Thermal Specifications 6.1.2 Thermal Metrology The minimum and maximum TTV case temperatures (T ) are specified in Table 6-1, CASE Table 6-2 and are measured at the geometric top center of the thermal test vehicle integrated heat spreader (IHS). Figure 6-2 illustrates the location where T CASE temperature measurements should be made.

  • Page 82: Processor Thermal Features

    6.2.1 Processor Temperature A new feature in the Intel Core™ i7 processor Extreme Edition and Intel Core™ i7 processor is a software readable field in the IA32_TEMPERATURE_TARGET register that contains the minimum temperature at which the TCC will be activated and PROCHOT# will be asserted.

  • Page 83: Frequency And Voltage Ordering

    Thermal Specifications 6.2.2.1 Frequency/VID Control When the Digital Temperature Sensor (DTS) reaches a value of 0 (DTS temperatures reported via PECI may not equal zero when PROCHOT# is activated, see Section 6.3 further details), the TCC will be activated and the PROCHOT# signal will be asserted. This indicates the processors' temperature has met or exceeded the factory calibrated trip temperature and it will take action to reduce the temperature.
  • Page 84 Unless immediate action is taken to resolve the failure, the processor will probably reach the Thermtrip temperature (see Section 6.2.3 Thermtrip Signal) within a short time. To prevent possible permanent silicon damage, Intel recommends removing power from the processor within ½ second of the Critical Temperature Flag being set 6.2.2.5...

  • Page 85: Thermtrip# Signal

    Introduction The Platform Environment Control Interface (PECI) is a one-wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices. The processor implements a PECI interface to allow communication of processor thermal and other information to other devices on the platform. The processor provides a digital thermal sensor (DTS) for fan speed control.

  • Page 86: Fan Speed Control With Digital Thermal Sensor

    Thermal Specifications 6.3.1.1 Fan Speed Control with Digital Thermal Sensor Fan speed control solutions use a value stored in the static variable, T . The DTS CONTROL temperature data which is delivered over PECI (in response to a GetTemp0() command) is compared to this T reference.

  • Page 87: Peci Specifications

    Thermal Specifications 6.3.2 PECI Specifications 6.3.2.1 PECI Device Address The PECI register resides at address 30h. 6.3.2.2 PECI Command Support The processor supports the PECI commands listed in Table 6-4. Table 6-4. Supported PECI Command Functions and Codes Command Code Comments Function This command targets a valid PECI device address followed by zero...

  • Page 88: Storage Conditions Specifications

    For functional operation, please refer to the processor case temperature specifications. These ratings apply to the Intel component and do not include the tray or packaging Failure to adhere to this specification can affect the long-term reliability of the processor Non operating storage limits post board attach: Storage condition limits for the component once attached to the application board are not specified.

  • Page 89: Features

    Chapter 2. Note that request to execute BIST is not selected by hardware but is passed across the Intel QPI link during initialization. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor;...

  • Page 90: Thread And Core Power State Descriptions

    MWAIT instruction. RESET# will cause the processor to initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal ® state or the C1 state. See the Intel 64 and IA-32 Architecture Software Developer's Manuals, Volume III: System Programmer's Guide for more information.

  • Page 91: Package Power State Descriptions

    Because the core’s caches are flushed, the processor keeps the core in the C3 state when the processor detects a snoop on the Intel QPI Link or when another logical processor in the same package accesses cacheable memory. The processor core will transition to the C0 state upon occurrence of an interrupt.

  • Page 92: Sleep States

    Features If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and for processors with an integrated memory controller, the DRAM will be put into self- refresh. 7.2.2.4 Package C6 State The package will enter the C6 low power state when all cores are in the C6 or lower power state and the processor has been granted permission by the other component(s) in the system to enter the C6 state.

  • Page 93: Enhanced Intel Speedstep Technology

    Features ® Enhanced Intel SpeedStep Technology The processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology: • Multiple voltage and frequency operating points provide optimal performance at the lowest power. • Voltage and frequency selection is software controlled by writing to processor MSRs: —...
  • Page 94 Features Datasheet...

  • Page 95: Boxed Processor Specifications

    Boxed Processor Specifications Introduction The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.

  • Page 96: Mechanical Specifications

    Boxed Processor Specifications Mechanical Specifications 8.2.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 8-1 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.

  • Page 97: Space Requirements For The Boxed Processor (Top View)

    Boxed Processor Specifications Figure 8-3. Space Requirements for the Boxed Processor (top view) NOTES: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 8-4. Space Requirements for the Boxed Processor (overall view) Datasheet...

  • Page 98: Boxed Processor Fan Heatsink Weight

    Boxed Processor Specifications 8.2.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 6 and the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). for details on the processor weight and heatsink requirements. 8.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly...

  • Page 99: Thermal Specifications

    Boxed Processor Specifications Table 8-1. Fan Heatsink Power and Signal Specifications Description Unit Notes +12 V: 12 volt fan power supply 10.8 13.2 - Peak steady-state fan current draw — — - Average steady-state fan current draw — — pulses per SENSE: SENSE frequency —...

  • Page 100: Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View)

    Boxed Processor Specifications Figure 8-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (top view) Figure 8-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side view) Datasheet...

  • Page 101: Variable Speed Fan

    Boxed Processor Specifications 8.4.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures.
  • Page 102 As processor power has increased the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage.

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