Intel i960 Jx Developer's Manual page 17

FIGURES
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Figure 1-1. i960 Jx Microprocessor Functional Block Diagram............................................ 1-3
Figure 2-1. Data Types and Ranges ...................................................................................... 2-1
Figure 2-2. Data Placement in Registers ............................................................................... 2-6
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Figure 3-1. i960 Jx Processor Programming Environment Elements .................................. 3-2
Figure 3-2. Memory Address Space .................................................................................... 3-13
Figure 3-3. Arithmetic Controls (AC) Register...................................................................... 3-18
Figure 3-4. Process Controls (PC) Register......................................................................... 3-21
Figure 4-1. Internal Data RAM and Register Cache .............................................................. 4-2
Figure 5-1. Machine-Level Instruction Formats...................................................................... 5-3
Figure 6-1. dcctl src1 and src/dst Formats ........................................................................... 6-41
Figure 6-2. Store Data Cache to Memory Output Format .................................................... 6-42
Figure 6-3. D-Cache Tag and Valid Bit Formats .................................................................. 6-43
icctl src1 and src/dst Formats ............................................................................ 6-59
Figure 6-4.
Figure 6-5. Store Instruction Cache to Memory Output Format ........................................... 6-61
Figure 6-6. I-Cache Set Data, Tag and Valid Bit Formats.................................................... 6-62
Figure 6-7. Src1 Operand Interpretation ............................................................................ 6-114
src/dst Interpretation for Breakpoint Resource Request .................................. 6-115
Figure 6-8.
Figure 7-1. Procedure Stack Structure and Local Registers.................................................. 7-3
Figure 7-2. Frame Spill........................................................................................................... 7-9
Figure 7-3. Frame Fill ........................................................................................................... 7-10
Figure 7-4. System Procedure Table ................................................................................... 7-16
Figure 7-5. Previous Frame Pointer Register (PFP) (r0)...................................................... 7-20
Figure 8-1. Fault-Handling Data Structures ........................................................................... 8-1
Figure 8-2. Fault Table and Fault Table Entries..................................................................... 8-5
Figure 8-3. Fault Record ........................................................................................................ 8-7
Figure 8-4. Storage of the Fault Record on the Stack............................................................ 8-8
Figure 9-1. 80960Jx Trace Controls (TC) Register ................................................................ 9-2
Figure 9-2. Breakpoint Control Register (BPCON)................................................................. 9-8
Figure 9-3. Data Address Breakpoint (DAB) Register Format ............................................. 9-10
Figure 9-4. Instruction Breakpoint (IPB) Register Format .................................................... 9-10
Figure 10-1. Timer Functional Diagram ................................................................................. 10-1
Figure 10-2. Timer Mode Register (TMR0, TMR1) ................................................................ 10-3
Figure 10-3. Timer Count Register (TCR0, TCR1)................................................................. 10-6
Figure 10-4. Timer Reload Register (TRR0, TRR1)............................................................... 10-7
Figure 10-5. Timer Unit State Diagram ................................................................................ 10-13
Figure 11-1. Interrupt Handling Data Structures .................................................................... 11-2
Figure 11-2. Interrupt Table ................................................................................................... 11-4
Figure 11-3. Storage of an Interrupt Record on the Interrupt Stack ....................................... 11-7
Figure 11-4. Dedicated Mode............................................................................................... 11-14
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