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GLOSSARY
Fault Table
An architecture-defined data structure that contains pointers to fault handling
procedures. Each fault table entry is associated with a particular fault type.
When the processor generates a fault, it uses the fault table to select the
proper fault handling procedure for the type of fault condition detected.
Fault
An event that the processor generates to indicate that, while executing the
program, a condition arose that could cause the processor to go down a
wrong and possibly disastrous path. One example of a fault condition is a
divisor operand of zero in a divide operation; another example is an
instruction with an invalid opcode.
Frame Pointer (FP) The address of the first byte in the current (topmost) stack frame of the
procedure stack. The FP is contained in global register g15.
Frame
See Stack Frame.
Global Registers
A set of 16 general-purpose registers (g0 through g15) whose contents are
preserved across procedure boundaries. Global registers are used for general
storage of data and addresses and for passing parameters between procedures.
Guarded Memory
A section of the processor that monitors all of the processor's memory
Unit (GMU)
transactions and can prevent accesses to predefined address regions or
warn the user program if accesses occur.
Hardware Reset
The assertion of the RESET# pin; equivalent to powerup.
IBR
See Initialization Boot Record.
IMI
See Initial Memory Image.
Imprecise Faults
Faults that are allowed to be generated out-of-order from where they
occur in the instruction stream. When an imprecise fault is generated, the
processor indicates the address of the faulting instruction, but it does not
guarantee that software can to recover from the fault and resume
execution of the program with no break in the program's control flow.
The NIF bit in the arithmetic controls register determines whether all
faults must be precise (1) or some faults are allowed to be imprecise (0).
Initialization Boot
One of three IMI components, IBR is the primary data structure required
Record (IBR)
to initialize the processor. IBR is 12-word structure which must be
located at address FFFF FF00H.
Initial Memory
Comprises the minimum set of data structures the processor needs to
Image (IMI)
initialize its system. Performs three functions for the processor: 1)
provides initial configuration information for the core and integrated
peripherals; 2) provides pointers to system data structures and the first
instruction to be executed after processor initialization; 3) provides
checksum words that the processor uses in self-test at startup. See also
IBR, PRCB and System Data Structures.
Glossary-2
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