Table of Contents
Advertisement
MACHINE-LEVEL INSTRUCTION FORMATS
This appendix describes the encoding format for instructions used by the i960
Included is a description of the four instruction formats and how the addressing modes relate to
these formats. Refer also to
C.1
GENERAL INSTRUCTION FORMAT
The i960 architecture defines four basic instruction encoding formats: REG, COBR, CTRL and
MEM (see
Figure
C-1). Each instruction uses one of these formats, which is defined by the
instruction's opcode field. All instructions are one word long and begin on word boundaries. MEM
format instructions are encoded in one of two sub-formats: MEMA or MEMB. MEMB supports an
optional second word to hold a displacement value. The following sections describe each format's
instruction word fields.
28
24
31
Opcode
(8 bits)
28
24
31
Opcode
(8 bits)
28
24
31
Opcode
(8 bits)
28
24
31
Opcode
(8 bits)
28
24
31
Opcode
(8 bits)
APPENDIX B, OPCODES AND EXECUTION
20
16
12
src/dst
src2
M
(5 bits)
(5 bits)
3
20
16
12
src1
src2
M
(5 bits)
(5 bits)
1
20
16
12
displacement
(22 bits)
20
16
12
src/dst
abase
X
(5 bits)
(5 bits)
20
16
12
src/dst
abase
X
(5 bits)
(5 bits)
Optional Displacement
Figure C-1. Instruction Formats
APPENDIX C
TIMES.
8
4
src1
M
M
Opcode
S
S
2
1
2
1
(4 bits)
(5 bits)
8
4
displacement
(11 bits)
8
4
8
4
Offset
0
(12 bits)
8
4
Scale
Index
1
X X
0
0
(3 bits)
(5 bits)
®
processors.
C
0
REG
0
S
T
COBR
2
0
CTRL
T
0
0
MEMA
MODE
0
MEMB
C-1
Advertisement
Table of Contents
