Table 3-2. Allowable Register Operands - Intel i960 Jx Developer's Manual

In cases where an instruction specifies a register number and multiple consecutive registers are
implied, the register number must be even when two registers are accessed (e.g., g0, g2) and an
integral multiple of 4, when 3 or 4 registers are accessed (e.g., g0, g4). When a register reference
for a source value is not properly aligned, the source value is undefined and an
OPERATION.INVALID_OPERAND fault is generated. When a register reference for a
destination value is not properly aligned, the registers to which the processor writes and the values
written are undefined. The processor then generates an OPERATION.INVALID_OPERAND fault.
The assembly language code in
alignment.
movl g3,g8
.
.
.
movl g4,g8
Global registers, local registers and literals are used directly as instruction operands.
instruction operands for each machine-level instruction format and the positions that can be filled
by each register or literal.
Instruction
Operand Field
Encoding
src1
src2
REG src/dst (as src )
src/dst (as dst )
src/dst (as both)
src/dst
MEM abase
index
src1
src2
COBR
dst
NOTES:
1. 1."X" denotes the register can be used as an operand in a particular instruction field.
COBR
2. The destination operands apply only to
Example 3-2 shows an example of correct and incorrect register
Example 3-2. Register Alignment
# Incorrect alignment - resulting value
# in registers g8 and g9 is
# unpredictable (non-aligned source)
# Correct alignment

Table 3-2. Allowable Register Operands

Local Register
X
X
X
X
X
X
X
X
X
X
X (2)
TEST
instructions.
PROGRAMMING ENVIRONMENT
Table 3-2
Operand (1)
Global
Literal
Register
X
X
X
X
X
X
X
X
X
X
X (2)
3
lists
X
X
X
3-5