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Byte Order (read-only)
0 = Little endian
1 = Big endian
Data Cache Enable
0 = Data caching disabled
1 = Data caching enabled
28
24
31
A
A
A
A
A
A
A
A
3
3
2
2
2
2
2
2
1
0
9
8
7
6
5
4
Reserved,
write to zero
Figure D-28. LMADR0:1 Logical Memory Template Starting Address Registers
Section 13.6, "Programming the Logical Memory Attributes" (pg. 13-8)
Logical Memory Template Enabled
0 = LMT disabled
1 = LMT enabled
28
24
31
M
M
M
M
M
M
M
M
A
A
A
A
A
A
A
A
3
3
2
2
2
2
2
2
1
0
9
8
7
6
5
4
Reserved,
write to zero
Figure D-29. LMMR0:1 (Logical Memory Mask Registers)
Section 13.6, "Programming the Logical Memory Attributes" (pg. 13-8)
REGISTER AND DATA STRUCTURES
20
16
A
A
A
A
A
A
A
A
A
A
A
2
2
2
2
1
1
1
1
1
1
1
3
2
1
0
9
8
7
6
5
4
3
20
16
M
M
M
M
M
M
M
M
M
M
M
A
A
A
A
A
A
A
A
A
A
A
2
2
2
2
1
1
1
1
1
1
1
3
2
1
0
9
8
7
6
5
4
3
12
A
1
2
8
4
Template Starting Address
12
M
A
1
2
8
4
Template Address Mask
D
D
B
C
E
E
N
0
L
M
T
E
0
D-25
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