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12.3.1.1
Initialization Boot Record (IBR)
The initialization boot record (IBR) is the primary data structure required to initialize the i960 Jx
processor. The IBR is a 12-word structure which must be located at address FEFF FF30H (see
Table
12-5). The IBR is made up of four components: the initial bus configuration data, the first
instruction pointer, the PRCB pointer and the bus confidence test checksum data.
Byte Physical Address
FEFF FF30H
FEFF FF31 to FEFF FF33
FEFF FF34H
FEFF FF35 to FEFF FF37
FEFF FF38H
FEFF FF39 to FEFF FF3B
FEFF FF3CH
FEFF FF3D to FEFF FF3F
FEFF FF40 to FEFF FF43
FEFF FF44 to FEFF FF47
FEFF FF48 to FEFF FF4B
FEFF FF4C to FEFF FF4F
FEFF FF50 to FEFF FF53
FEFF FF54 to FEFF FF57
FEFF FF58 to FEFF FF5B
FEFF FF5C to FEFF FF5F
When the processor reads the IMI during initialization, it must know the bus characteristics of
external memory where the IMI is located. Specifically, it must know the bus width and endianism
for the remainder of the IMI. At initialization, the processor sets the PMCON register to an 8-bit
bus width. The processor then needs to form the initial DLMCON and PMCON14_15 registers so
that the memory containing the IBR can be accessed correctly. The lowest-order byte of each of
the IBR's first 4 words are used to form the register values. On the i960 Jx processor, the bytes at
FEFF FF30 and FEFF FF34 are not needed, so the processor starts fetching at address FEFF FF38.
The loading of these registers is shown in the pseudo-code flow in
INITIALIZATION AND SYSTEM REQUIREMENTS
Table 12-5. Initialization Boot Record
PMCON14_15, byte 0
Reserved
PMCON14_15, byte 1
Reserved
PMCON14_15, byte 2
Reserved
PMCON14_15, byte 3
Reserved
First Instruction Pointer
PRCB Pointer
Bus Confidence Self-Test Check Word 0
Bus Confidence Self-Test Check Word 1
Bus Confidence Self-Test Check Word 2
Bus Confidence Self-Test Check Word 3
Bus Confidence Self-Test Check Word 4
Bus Confidence Self-Test Check Word 5
Description
Example
12-1.
12
12-13
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