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INSTRUCTION SET REFERENCE
6.2.8
b, bx
Mnemonic:
b
bx
Format:
b
bx
Branches to the specified target.
Description:
With the
23
-2
to (2
assembler, targ operand must be a label which specifies target instruction's
IP.
performs the same operation as
bx
farther than -2
an effective address, which allows the full range of addressing modes to be
used to specify target instruction's IP. The "IP + displacement" addressing
mode allows the instruction to be IP-relative. Indirect branching can be
performed by placing target address in a register then using a register-indirect
addressing mode.
Refer to
information on this subject.
Action:
b:
temp[31:2] = sign_extension(targ[23:2]);
IP[31:2] = IP[31:2] + temp[31:2];
IP[1:0] = 0;
bx:
IP[31:2] = effective_address(targ[31:2]);
IP[1:0] = 0;
STANDARD
Faults:
Example:
b xyz
bx 1332 (ip)
# this example uses IP-relative addressing
Opcode:
b
bx
See Also:
bal, balx, BRANCH<cc>, COMPARE AND BRANCH<cc>, bbc, bbs
6-16
Branch
Branch Extended
targ
disp
targ
mem
instruction, IP specified with targ operand can be no farther than
b
23
- 4) bytes from current IP. When using the Intel i960 processor
23
23
to (2
- 4) bytes from current IP. Here, the target operand is
section 2.3, "MEMORY ADDRESSING MODES" (pg. 2-6)
Refer to
# IP
# IP
08H
CTRL
84H
MEM
except the target instruction can be
b
section 6.1.6, "Faults" (pg.
xyz;
IP + 8 + 1332;
for
6-5).
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