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10.1.3
Timer Reload Register (TRR0, TRR1)
The Timer Reload Register (TRRx;
count. The timer loads the reload count value into TCRx when TMRx.reload is set (1),
TMRx.enable is set (1) and TCRx equals zero.
As with TCRx, the valid programmable range is from 1H to FFFF FFFFH. Avoid programming a
value of 0, as it may prevent TINTx from asserting continuously. (See
"UNCOMMON TCRX AND TRRX CONDITIONS" (pg. 10-12)
User software can access TRRx whether the timer is running or stopped. Bit 3 of TMRx
determines read/write control (see
software reset.
Timer Auto-Reload Value - TRRx.d31:0
D31:0
28
Timer Reload Register (TRR0, TRR1)
Figure 10-4. Timer Reload Register (TRR0, TRR1)
10.2
TIMER OPERATION
This section summarizes timer operation and describes load/store access latency for the timer registers.
10.2.1
Basic Timer Operation
Each timer has a programmable enable bit in its control register (TMRx.enable) to start and stop
counting. The supervisor (TMRx.sup) bit controls write access to the enable bit. This allows the
programmer to prevent user mode tasks from enabling or disabling the timer. Once the timer is
enabled, the value stored in the Timer Count Register (TCRx) decrements every Timer Clock
(TCLOCK) cycle. TCLOCK is determined by the Timer Input Clock Select (TMRx.csel) bit
setting. The countdown rate can be set to equal the bus clock frequency, or the bus clock rate
divided by 2, 4 or 8. Setting TCLOCK to a slower rate lets the user specify a longer count period
with the same 32-bit TCRx value.
Figure
10-4) is a 32-bit register that contains the timer's reload
section
10.1.1.4). TRRx value is undefined after hardware or
24
20
16
for more information.)
12
8
4
TIMERS
section 10.5,
0
10
10-7
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