Table of Contents
Advertisement
INITIALIZATION AND SYSTEM REQUIREMENTS
RESET
Internal Self-Test
FAIL
12.2.2.4
IMI Alignment Check and System Error
The alignment check during initialization for data structures within the IMI ensures that the
PRCB, control table, interrupt table, system-procedure table, and fault table are aligned to word
boundaries. Normal processor operation is not possible without the alignment of these key data
structures. The alignment check is one case where a System Error could occur.
The other case of System Error can occur during regular operation when generation of an override
fault incurs a fault. The sequence of events leading up to this case is quite uncommon.
When a System Error is detected, the FAIL pin is asserted, a fail code message is driven onto the
address bus, and the processor stops execution at the point of failure. The only way to resume normal
operation of the processor is to perform a reset operation. Because System Error generation can
occur sometime after the BUS confidence test and even after initialization during normal processor
operation, the FAIL pin will be at a logic one before the detection of a System Error.
12.2.2.5
FAIL Code
The processor uses only one read bus transaction to signal the fail code message; the address of the
bus transaction is the fail code itself. The fail code is of the form: 0xfeffffnn; bits 6 to 0 contain a
mask recording the possible failures. Bit 7, when one, indicates the mask contains failures from
Built-In Self-Test (BIST); when zero, the mask indicates other failures. The fail codes are shown
in
Table 12-3
and
Table
12-4.
12-8
Internal Self-Test Status
PASS
Bus Confidence Test
FAIL
Figure 12-3. FAIL Sequence
Bus Confidence
Test Status
PASS
FAIL
Advertisement
Table of Contents
