C.5.1 Mema Format Addressing; Table C-6. Addressing Modes For Mem Format Instructions - Intel i960 Jx Developer's Manual

The mode field determines the address mode used for the instruction.
addressing modes for the two MEM-format encodings. Fields used in these addressing modes are
described in the following sections.

Table C-6. Addressing Modes for MEM Format Instructions

Format MODE Addressing Mode
00 Absolute Offset
MEMA
10 Register Indirect with Offset
0100 Register Indirect
0101 IP with Displacement
0110 Reserved
0111 Register Indirect with Index
1100 Absolute Displacement
MEMB
Register Indirect with
1101
Displacement
1110 Index with Displacement
Register Indirect with Index and
1111
Displacement
:
NOTE
In these address computations, a field in parentheses indicates that the value in the specified regis-
ter is used in the computation.
Usage of a reserved encoding may cause generation of an OPERATION.INVALID_OPCODE
fault.
C.5.1 MEMA Format Addressing
The MEMA format provides two addressing modes:
• Absolute offset
• Register indirect with offset
The offset field specifies an unsigned byte offset from 0 to 4096. The abase field specifies a global
or local register that contains an address in memory.
For the absolute-offset addressing mode (MODE = 00), the processor interprets the offset field as
an offset from byte 0 of the current process address space; the abase field is ignored. Using this
addressing mode along with the
loaded into a register.
MACHINE-LEVEL INSTRUCTION FORMATS
Address Computation
offset
(abase) + offset
(abase)
(IP) + displacement + 8
reserved
(abase) + (index) * 2
displacement
(abase) + displacement
scale
(index) * 2
(abase) + (index) * 2
instruction allows a constant in the range 0 to 4096 to be
lda
Table C-6 summarizes the
# of Instr
scale
+ displacement
scale
+ displacement
C
Words
1
1
1
2
NA
1
2
2
2
2
C-5