Intel i960 Jx Developer's Manual page 395

Microprocessor
Table of Contents

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Example 12-4. Startup Routine (init.s)
/*----------------------------------------------------------*/
/*
init.s
/*----------------------------------------------------------*/
/* initial PRCB
*/
.globl
_rom_prcb
.align 4 /* or .align 2 */
_rom_prcb:
.word
boot_flt_table
.word
_boot_control_table #
.word
0x00001000
.word
0x40000000
.word
boot_intr_table
.word
rom_sys_proc_table
.word
0
.word
_intr_stack
.word
0x00000000
.word
0x00001200
/* ROM system procedure table */
.equ
supervisor_proc, 2
.text
.align 6 /* or .align 2 or .align 4 */
rom_sys_proc_table:
.space
12
.word
_supervisor_stack
.space
32
.word
_default_sysproc
.word
_default_sysproc
.word
_default_sysproc
.word
_default_sysproc
.word
_default_sysproc
.word
_default_sysproc
.word
_default_sysproc
.word
_fault_handler + supervisor_proc
.word
_default_sysproc
.space
251*4
/* Fault Table */
.equ
syscall, 2
.equ
fault_proc, 7
.text
.align
4
boot_flt_table:
.word
(fault_proc<<2) + syscall
.word
0x27f
.word
(fault_proc<<2) + syscall
.word
0x27f
.word
(fault_proc<<2) + syscall
.word
0x27f
INITIALIZATION AND SYSTEM REQUIREMENTS
(Sheet 1 of 4)
#
0 - Fault Table
4 - Control Table
#
8 - AC reg mask overflow fault
# 12 - Flt CFG
# 16 - Interrupt Table
# 20 - System Procedure Table
# 24 - Reserved
# 28 - Interrupt Stack Pointer
# 32 - Inst. Cache - enable cache
# 36 - Register Cache Configuration
# Reserved
# Supervisor stack pointer
# Preserved
# sysproc 0
# sysproc 1
# sysproc 2
# sysproc 3
# sysproc 4
# sysproc 5
# sysproc 6
# sysproc 7
# sysproc 8
# sysproc 9-259
# 0-Parallel Fault
# 1-Trace Fault
# 2-Operation Fault
*/
12
12-25

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