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MEMORY CONFIGURATION
The Default Logical Memory Configuration (DLMCON) register is shown in
BCU uses the parameters in the DLMCON register when the current access does not fall within
one of the two logical memory templates (LMTs). Notice the byte ordering is controlled for the
entire address space by programming the DLMCON register.
Byte Order
0 = Little endian
1 = Big endian
Data Cache Enabled
0 = Data caching disabled
1 = Write-through caching enabled
28
24
31
Reserved,
write to zero
Mnemonic
Bit/Bit Field Name
DCEN
Data Cache Enable
Big Endian Byte
BE
Order
Figure 13-6. Default Logical Memory Configuration Register (DLMCON)
13-10
20
16
12
Bit Position(s)
Controls data caching for areas not within
other logical memory templates.
0 = Data caching disabled
1
1 = Write-through caching enabled
Instruction caching is never affected by this
bit.
Controls byte order for all accesses, both
instruction and data, to memory.
0
0 = Little endian
1 = Big endian
Figure
13-6. The
D
C
B
E
E
N
8
4
0
Function
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