Table 2-1. Memory Contents For Little And Big Endian Example; Table 2-2. Byte Ordering For Little And Big Endian Accesses - Intel i960 Jx Developer's Manual

For example, Table 2-1 shows eight bytes of data in memory.
between little and big endian accesses for byte, short, word and long-word data.
the resultant data placement in registers.
Once data is read into registers, byte order is no longer relevant. The lowest significant bit is
always bit 0. The most significant bit is always bit 31 for words, bit 15 for short words, and bit 7
for bytes.
Byte ordering affects the way the i960 Jx processor handles bus accesses. See
"Selecting the Byte Order" (pg. 13-12)

Table 2-1. Memory Contents for Little and Big Endian Example

ADDRESS
1000H
1001H
1002H
1003H
1004H
1005H
1006H
1007H

Table 2-2. Byte Ordering for Little and Big Endian Accesses

Access
Byte at 1000H
ldob 0x1000, r3
Short at 1002H
ldos 0x1002, r3
Word at 1000H
ld
Long-Word at 1000H
ldl
DATA TYPES AND MEMORY ADDRESSING MODES
for more information.
Register Contents
Example
(Little Endian)
0x1000, r3
78563412H (r4)
0x1000, r4
F0DEBC9AH (r5)
Table 2-2 shows the differences
Figure 2-2
section 13.6.2,
DATA
12H
34H
56H
78H
9AH
BCH
DEH
F0H
Register Contents
(Big Endian)
12H
7856H
78563412H 12345678H
12345678H (r4)
9ABCDEF0H (r5)
shows
2
12H
5678H
2-5