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CHAPTER 11
INTERRUPTS
®
This chapter describes the i960
processor core architecture interrupt mechanism and the i960 Jx
processor interrupt controller. Key topics include the i960 Jx processor's facilities for requesting
and posting interrupts, the programmer's interface to the on-chip interrupt controller, latency and
how to optimize interrupt performance.
11.1
OVERVIEW
An interrupt is an event that causes a temporary break in program execution so the processor can
handle another task. Interrupts commonly request I/O services or synchronize the processor with
some external hardware activity. For interrupt handler portability across the i960 processor family,
the architecture defines a consistent interrupt state and interrupt-priority-handling mechanism. To
manage and prioritize interrupt requests in parallel with processor execution, the i960 Jx processor
provides an on-chip programmable interrupt controller.
Requests for interrupt service come from many sources. These requests are prioritized so that
instruction execution is redirected only if an interrupt request is of higher priority than that of the
executing task. On the i960 Jx processor, interrupt requests may originate from external hardware
sources, internal timer unit sources or from software. External interrupts are detected with the
chip's 8-bit interrupt port and with a dedicated Non-Maskable Interrupt (NMI) input. Interrupt
11
requests originate from software by the
sysctl
instruction. To manage and prioritize all possible
interrupts, the processor integrates an on-chip programmable interrupt controller. Integrated
interrupt controller configuration and operation is described in
section 11.7, "EXTERNAL
INTERFACE DESCRIPTION" (pg.
11-18).
When the processor is redirected to service an interrupt, it uses a vector number that accompanies
the interrupt request to locate the vector entry in the interrupt table. From that entry, it gets an
address to the first instruction of the selected interrupt procedure. The processor then makes an
implicit call to that procedure.
When the interrupt call is made, the processor uses a dedicated interrupt stack. The processor
creates a new frame for the interrupt on this stack and a new set of local registers is allocated to the
interrupt procedure. The interrupted program's current state is also saved.
Upon return from the interrupt procedure, the processor restores the interrupted program's state, switches
back to the stack that the processor was using prior to the interrupt and resumes program execution.
11-1
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