Intel BX80605I7870 - Core i7 2.93 GHz Processor Datasheet
  1. Manuals
  2. Brands
  3. Intel Manuals
  4. Computer Hardware
  5. BX80605I7870 - Core i7 2.93 GHz Processor
  6. Datasheet
Intel BX80605I7870 - Core i7 2.93 GHz Processor Datasheet

Intel BX80605I7870 - Core i7 2.93 GHz Processor Datasheet

Data sheet
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
®
Intel
Core™ i7 Processor Extreme
®
Edition and Intel
Core™ i7
Processor
Datasheet, Volume 2
November 2008
Document Number: 320835-002

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the BX80605I7870 - Core i7 2.93 GHz Processor and is the answer not in the manual?

Questions and answers

Related Manuals for Intel BX80605I7870 - Core i7 2.93 GHz Processor

Summary of Contents for Intel BX80605I7870 - Core i7 2.93 GHz Processor

  • Page 1 ® Intel Core™ i7 Processor Extreme ® Edition and Intel Core™ i7 Processor Datasheet, Volume 2 November 2008 Document Number: 320835-002...
  • Page 2 Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see www.intel.com. Intel, Xeon, Enhanced Intel SpeedStep Technology and the Intel logo are trademarks of Intel Corporation in the United States and other countries.

  • Page 3: Table Of Contents

    SAD_DRAM_RULE_4, SAD_DRAM_RULE_5 SAD_DRAM_RULE_6, SAD_DRAM_RULE_7 ..........46 2.6.7 SAD_INTERLEAVE_LIST_0, SAD_INTERLEAVE_LIST_1 SAD_INTERLEAVE_LIST_2, SAD_INTERLEAVE_LIST_3 SAD_INTERLEAVE_LIST_4, SAD_INTERLEAVE_LIST_5 SAD_INTERLEAVE_LIST_6, SAD_INTERLEAVE_LIST_7 ....... 47 Intel QPI Link Registers..................48 2.7.1 QPI_QPILCL_L0, QPI_QPILCL_L1 ............48 Integrated Memory Controller Control Registers ............ 48 2.8.1 MC_CONTROL ..................48 2.8.2 MC_STATUS ..................50 2.8.3...
  • Page 4 2.9.2 TAD_INTERLEAVE_LIST_0, TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_2, TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_4, TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_6, TAD_INTERLEAVE_LIST_7........59 2.10 Integrated Memory Controller Channel Control Registers.........60 2.10.1 MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_1_DIMM_RESET_CMD MC_CHANNEL_2_DIMM_RESET_CMD ............60 2.10.2 MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_1_DIMM_INIT_CMD MC_CHANNEL_2_DIMM_INIT_CMD ............61 2.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_1_DIMM_INIT_PARAMS MC_CHANNEL_2_DIMM_INIT_PARAMS .............62 2.10.4 MC_CHANNEL_0_DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS MC_CHANNEL_2_DIMM_INIT_STATUS .............63 2.10.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD MC_CHANNEL_2_DDR3CMD..............64 2.10.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT...
  • Page 5 2.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD......... 74 2.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD......... 75 2.10.21 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_WR ........75 2.10.22 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_WR ........75 2.10.23 MC_CHANNEL_0_WAQ_PARAMS MC_CHANNEL_1_WAQ_PARAMS MC_CHANNEL_2_WAQ_PARAMS ............. 76 2.10.24 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS MC_CHANNEL_2_SCHEDULER_PARAMS ........... 77 2.10.25 MC_CHANNEL_0_MAINTENANCE_OPS MC_CHANNEL_1_MAINTENANCE_OPS MC_CHANNEL_2_MAINTENANCE_OPS ............. 77 2.10.26 MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_1_TX_BG_SETTINGS MC_CHANNEL_2_TX_BG_SETTINGS ............
  • Page 6 2.10.39 Error Injection Implementation ...............84 2.11 Integrated Memory Controller Channel Address Registers........85 2.11.1 MC_DOD_CH0_0, MC_DOD_CH0_1, MC_DOD_CH0_2 ........85 2.11.2 MC_DOD_CH1_0, MC_DOD_CH1_1, MC_DOD_CH1_2 ........86 2.11.3 MC_DOD_CH2_0, MC_DOD_CH2_1, MC_DOD_CH2_2 ........87 2.11.4 MC_SAG_CH0_0, MC_SAG_CH0_1, MC_SAG_CH0_2 MC_SAG_CH0_3, MC_SAG_CH0_4, MC_SAG_CH0_5 MC_SAG_CH0_6, MC_SAG_CH0_7, MC_SAG_CH1_0 MC_SAG_CH1_1, MC_SAG_CH1_2, MC_SAG_CH1_3 MC_SAG_CH1_4, MC_SAG_CH1_5, MC_SAG_CH1_6 MC_SAG_CH1_7, MC_SAG_CH2_0, MC_SAG_CH2_1 MC_SAG_CH2_2, MC_SAG_CH2_3, MC_SAG_CH2_4...
  • Page 7 MC_RIR_WAY_CH2_6, MC_RIR_WAY_CH2_7 MC_RIR_WAY_CH2_8, MC_RIR_WAY_CH2_9 MC_RIR_WAY_CH2_10, MC_RIR_WAY_CH2_11 MC_RIR_WAY_CH2_12, MC_RIR_WAY_CH2_13 MC_RIR_WAY_CH2_14, MC_RIR_WAY_CH2_15 MC_RIR_WAY_CH2_16, MC_RIR_WAY_CH2_17 MC_RIR_WAY_CH2_18, MC_RIR_WAY_CH2_19 MC_RIR_WAY_CH2_20, MC_RIR_WAY_CH2_21 MC_RIR_WAY_CH2_22, MC_RIR_WAY_CH2_23 MC_RIR_WAY_CH2_24, MC_RIR_WAY_CH2_25 MC_RIR_WAY_CH2_26, MC_RIR_WAY_CH2_27 MC_RIR_WAY_CH2_28, MC_RIR_WAY_CH2_29 MC_RIR_WAY_CH2_30, MC_RIR_WAY_CH2_31 ........92 2.13 Memory Thermal Control ..................93 2.13.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL1 MC_THERMAL_CONTROL2..............93 2.13.2 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1 MC_THERMAL_STATUS2 ................
  • Page 8 Device 0, Function 0: Generic Non-core Registers ..........19 Device 0, Function 1: System Address Decoder Registers ........20 Device 2, Function 0: Intel QPI Link 0 Registers .............21 Device 2, Function 1: Intel QPI Physical 0 Registers ..........22 Device 3, Function 0: Integrated Memory Controller Registers .........23 Device 3, Function 1: Target Address Decoder Registers .........24...

  • Page 9: Revision History

    Revision History Revision Description Date Number -001 Initial release. November 2008 -002 Updated section 2.2 and Table 2.3. November 2008 Datasheet...
  • Page 10 Datasheet...

  • Page 11: Introduction

    45 nm process technology. Processor features vary by component and include up to two Intel QuickPath Interconnect point to point links capable of up to 6.4 GT/s, up to 8 MB of shared cache, and an integrated memory controller.
  • Page 12 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of Intel 64. Further details on Intel 64 architecture and programming model can be found at http://developer.intel.com/technology/intel64/. ®...

  • Page 13: References

    Material and concepts available in the following documents may be beneficial when reading this document. Table 1-1. References Document Location ® ® Intel Core™ i7 Processor Extreme Edition and Intel Core™ i7 Processor http://download.intel.com Specification Update /design/processor/specup dt/320836.pdf ® ® http://download.intel.com Intel Core™...
  • Page 14 Introduction Datasheet...

  • Page 15: Register Description

    Register Description Register Description The processor supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism in the PCI specification as defined in the PCI Local Bus Specification, Revision 2.3, as well as the PCI Express* enhanced configuration mechanism as specified in the PCI Express Base Specification, Revision 1.1.

  • Page 16: Platform Configuration Structure

    8, 16, or 32 bits in size). Writes to “Reserved” registers have no effect on the processor. Registers that are marked as “Intel Reserved” must not be modified by system software. Writes to “Intel Reserved” registers may cause system failure. Reads to “Intel Reserved”...

  • Page 17: Device Mapping

    Table 2-1. Functions Specifically Handled by the Processor Component Register Group Device Function 2C41h Intel QuickPath Architecture Generic Non-core Registers Intel QuickPath Architecture System Address Decoder 2C01h Intel QPI Link 0 2C10h 2C11 Intel QPI Physical 0 2C18h...

  • Page 18: Detailed Configuration Space Maps

    Register Description Detailed Configuration Space Maps Table 2-2. Device 0, Function 0: Generic Non-core Registers PCISTS PCICMD SVID Datasheet...

  • Page 19: Device 0, Function 1: System Address Decoder Registers

    Register Description Table 2-3. Device 0, Function 1: System Address Decoder Registers SAD_DRAM_RULE_0 PCISTS PCICMD SAD_DRAM_RULE_1 SAD_DRAM_RULE_2 SAD_DRAM_RULE_3 SAD_DRAM_RULE_4 SAD_DRAM_RULE_5 SAD_DRAM_RULE_6 SAD_DRAM_RULE_7 SVID SAD_PAM0123 SAD_INTERLEAVE_LIST_0 SAD_PAM456 SAD_INTERLEAVE_LIST_1 SAD_HEN SAD_INTERLEAVE_LIST_2 SAD_SMRAM SAD_INTERLEAVE_LIST_3 SAD_PCIEXBAR SAD_INTERLEAVE_LIST_4 SAD_INTERLEAVE_LIST_5 SAD_INTERLEAVE_LIST_6 SAD_INTERLEAVE_LIST_7 Datasheet...

  • Page 20: Device 2, Function 0: Intel Qpi Link 0 Registers

    Register Description Table 2-4. Device 2, Function 0: Intel QPI Link 0 Registers PCISTS PCICMD SVID QPI_QPILCL_L0 Datasheet...

  • Page 21: Device 2, Function 1: Intel Qpi Physical 0 Registers

    Register Description Table 2-5. Device 2, Function 1: Intel QPI Physical 0 Registers PCISTS PCICMD SVID Datasheet...

  • Page 22: Device 3, Function 0: Integrated Memory Controller Registers

    Register Description Table 2-6. Device 3, Function 0: Integrated Memory Controller Registers PCISTS PCICMD SVID MC_CONTROL MC_STATUS MC_SMI_SPARE_DIMM_ERROR_STATUS MC_SMI_SPARE_CNTRL MC_RESET_CONTROL MC_CHANNEL_MAPPER MC_MAX_DOD MC_RD_CRDT_INIT MC_CRDT_WR_THLD MC_SCRUBADDR_LO MC_SCRUBADDR_HI Datasheet...

  • Page 23: Device 3, Function 1: Target Address Decoder Registers

    Register Description Table 2-7. Device 3, Function 1: Target Address Decoder Registers TAD_DRAM_RULE_0 PCISTS PCICMD TAD_DRAM_RULE_1 TAD_DRAM_RULE_2 TAD_DRAM_RULE_3 TAD_DRAM_RULE_4 TAD_DRAM_RULE_5 TAD_DRAM_RULE_6 TAD_DRAM_RULE_7 SVID TAD_INTERLEAVE_LIST_0 TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_2 TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_4 TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_6 TAD_INTERLEAVE_LIST_7 Datasheet...

  • Page 24: Device 4, Function 0: Integrated Memory Controller Channel

    Register Description Table 2-8. Device 4, Function 0: Integrated Memory Controller Channel 0 Control Registers MC_CHANNEL_0_RANK_TIMING_A PCISTS PCICMD MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_0_BANK_TIMING MC_CHANNEL_0_REFRESH_TIMING MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_0_ZQ_TIMING MC_CHANNEL_0_RCOMP_PARAMS MC_CHANNEL_0_ODT_PARAMS1 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD SVID MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_0_WAQ_PARAMS MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_0_MAINTENANCE_OPS MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_0_RX_BGF_SETTINGS MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_0_ROUND_TRIP_LATENCY MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_0_PAGETABLE_PARAMS1...

  • Page 25: Device 4, Function 1: Integrated Memory Controller Channel

    Register Description Table 2-9. Device 4, Function 1: Integrated Memory Controller Channel 0 Address Registers MC_SAG_CH0_0 PCISTS PCICMD MC_SAG_CH0_1 MC_SAG_CH0_2 MC_SAG_CH0_3 MC_SAG_CH0_4 MC_SAG_CH0_5 MC_SAG_CH0_6 MC_SAG_CH0_7 SVID MC_DOD_CH0_0 MC_DOD_CH0_1 MC_DOD_CH0_2 Datasheet...

  • Page 26: Device 4, Function 2: Integrated Memory Controller Channel

    Register Description Table 2-10. Device 4, Function 2: Integrated Memory Controller Channel 0 Rank Registers MC_RIR_WAY_CH0_0 PCISTS PCICMD MC_RIR_WAY_CH0_1 MC_RIR_WAY_CH0_2 MC_RIR_WAY_CH0_3 MC_RIR_WAY_CH0_4 MC_RIR_WAY_CH0_5 MC_RIR_WAY_CH0_6 MC_RIR_WAY_CH0_7 MC_RIR_WAY_CH0_8 MC_RIR_WAY_CH0_9 MC_RIR_WAY_CH0_10 SVID MC_RIR_WAY_CH0_11 MC_RIR_WAY_CH0_12 MC_RIR_WAY_CH0_13 MC_RIR_WAY_CH0_14 MC_RIR_WAY_CH0_15 MC_RIR_LIMIT_CH0_0 MC_RIR_WAY_CH0_16 MC_RIR_LIMIT_CH0_1 MC_RIR_WAY_CH0_17 MC_RIR_LIMIT_CH0_2 MC_RIR_WAY_CH0_18 MC_RIR_LIMIT_CH0_3 MC_RIR_WAY_CH0_19 MC_RIR_LIMIT_CH0_4...

  • Page 27: Device 4, Function 3: Integrated Memory Controller Channel

    Register Description Table 2-11. Device 4, Function 3: Integrated Memory Controller Channel 0 Thermal Control Registers MC_COOLING_COEF0 PCISTS PCICMD MC_CLOSED_LOOP0 MC_THROTTLE_OFFSET0 MC_RANK_VIRTUAL_TEMP0 MC_DDR_THERM_COMMAND0 MC_DDR_THERM_STATUS0 SVID MC_THERMAL_CONTROL0 MC_THERMAL_STATUS0 MC_THERMAL_DEFEATURE0 MC_THERMAL_PARAMS_A0 MC_THERMAL_PARAMS_B0 Datasheet...

  • Page 28: Device 5, Function 0: Integrated Memory Controller Channel

    Register Description Table 2-12. Device 5, Function 0: Integrated Memory Controller Channel 1 Control Registers MC_CHANNEL_1_RANK_TIMING_A PCISTS PCICMD MC_CHANNEL_1_RANK_TIMING_B MC_CHANNEL_1_BANK_TIMING MC_CHANNEL_1_REFRESH_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_1_ZQ_TIMING MC_CHANNEL_1_RCOMP_PARAMS MC_CHANNEL_1_ODT_PARAMS1 MC_CHANNEL_1_ODT_PARAMS2 MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD SVID MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_1_WAQ_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS MC_CHANNEL_1_MAINTENANCE_OPS MC_CHANNEL_1_TX_BG_SETTINGS MC_CHANNEL_1_RX_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS MC_CHANNEL_1_DIMM_RESET_CMD MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_1_DIMM_INIT_CMD MC_CHANNEL_1_ROUND_TRIP_LATENCY MC_CHANNEL_1_DIMM_INIT_PARAMS MC_CHANNEL_1_PAGETABLE_PARAMS1...

  • Page 29: Device 5, Function 1: Integrated Memory Controller Channel

    Register Description Table 2-13. Device 5, Function 1: Integrated Memory Controller Channel 1 Address Registers MC_SAG_CH1_0 PCISTS PCICMD MC_SAG_CH1_1 MC_SAG_CH1_2 MC_SAG_CH1_3 MC_SAG_CH1_4 MC_SAG_CH1_5 MC_SAG_CH1_6 MC_SAG_CH1_7 SVID MC_DOD_CH1_0 MC_DOD_CH1_1 MC_DOD_CH1_2 Datasheet...

  • Page 30: Device 5, Function 2: Integrated Memory Controller Channel

    Register Description Table 2-14. Device 5, Function 2: Integrated Memory Controller Channel 1 Rank Registers MC_RIR_WAY_CH1_0 PCISTS PCICMD MC_RIR_WAY_CH1_1 MC_RIR_WAY_CH1_2 MC_RIR_WAY_CH1_3 MC_RIR_WAY_CH1_4 MC_RIR_WAY_CH1_5 MC_RIR_WAY_CH1_6 MC_RIR_WAY_CH1_7 MC_RIR_WAY_CH1_8 MC_RIR_WAY_CH1_9 MC_RIR_WAY_CH1_10 SVID MC_RIR_WAY_CH1_11 MC_RIR_WAY_CH1_12 MC_RIR_WAY_CH1_13 MC_RIR_WAY_CH1_14 MC_RIR_WAY_CH1_15 MC_RIR_LIMIT_CH1_0 MC_RIR_WAY_CH1_16 MC_RIR_LIMIT_CH1_1 MC_RIR_WAY_CH1_17 MC_RIR_LIMIT_CH1_2 MC_RIR_WAY_CH1_18 MC_RIR_LIMIT_CH1_3 MC_RIR_WAY_CH1_19 MC_RIR_LIMIT_CH1_4...

  • Page 31: Device 5, Function 3: Integrated Memory Controller Channel

    Register Description Table 2-15. Device 5, Function 3: Integrated Memory Controller Channel 1 Thermal Control Registers MC_COOLING_COEF1 PCISTS PCICMD MC_CLOSED_LOOP1 MC_THROTTLE_OFFSET1 MC_RANK_VIRTUAL_TEMP1 MC_DDR_THERM_COMMAND1 MC_DDR_THERM_STATUS1 SVID MC_THERMAL_CONTROL1 MC_THERMAL_STATUS1 MC_THERMAL_DEFEATURE1 MC_THERMAL_PARAMS_A1 MC_THERMAL_PARAMS_B1 Datasheet...

  • Page 32: Device 6, Function 0: Integrated Memory Controller Channel

    Register Description Table 2-16. Device 6, Function 0: Integrated Memory Controller Channel 2 Control Registers MC_CHANNEL_2_RANK_TIMING_A PCISTS PCICMD MC_CHANNEL_2_RANK_TIMING_B MC_CHANNEL_2_BANK_TIMING MC_CHANNEL_2_REFRESH_TIMING MC_CHANNEL_2_CKE_TIMING MC_CHANNEL_2_ZQ_TIMING MC_CHANNEL_2_RCOMP_PARAMS MC_CHANNEL_2_ODT_PARAMS1 MC_CHANNEL_2_ODT_PARAMS2 MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD SVID MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_2_WAQ_PARAMS MC_CHANNEL_2_SCHEDULER_PARAMS MC_CHANNEL_2_MAINTENANCE_OPS MC_CHANNEL_2_TX_BG_SETTINGS MC_CHANNEL_2_RX_BGF_SETTINGS MC_CHANNEL_2_EW_BGF_SETTINGS MC_CHANNEL_2_DIMM_RESET_CMD MC_CHANNEL_2_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_2_DIMM_INIT_CMD MC_CHANNEL_2_ROUND_TRIP_LATENCY MC_CHANNEL_2_DIMM_INIT_PARAMS MC_CHANNEL_2_PAGETABLE_PARAMS1...

  • Page 33: Device 6, Function 1: Integrated Memory Controller Channel

    Register Description Table 2-17. Device 6, Function 1: Integrated Memory Controller Channel 2 Address Registers MC_SAG_CH2_0 PCISTS PCICMD MC_SAG_CH2_1 MC_SAG_CH2_2 MC_SAG_CH2_3 MC_SAG_CH2_4 MC_SAG_CH2_5 MC_SAG_CH2_6 MC_SAG_CH2_7 SVID MC_DOD_CH2_0 MC_DOD_CH2_1 MC_DOD_CH2_2 Datasheet...

  • Page 34: Device 6, Function 2: Integrated Memory Controller Channel

    Register Description Table 2-18. Device 6, Function 2: Integrated Memory Controller Channel 2 Rank Registers MC_RIR_WAY_CH2_0 PCISTS PCICMD MC_RIR_WAY_CH2_1 MC_RIR_WAY_CH2_2 MC_RIR_WAY_CH2_3 MC_RIR_WAY_CH2_4 MC_RIR_WAY_CH2_5 MC_RIR_WAY_CH2_6 MC_RIR_WAY_CH2_7 MC_RIR_WAY_CH2_8 MC_RIR_WAY_CH2_9 MC_RIR_WAY_CH2_10 SVID MC_RIR_WAY_CH2_11 MC_RIR_WAY_CH2_12 MC_RIR_WAY_CH2_13 MC_RIR_WAY_CH2_14 MC_RIR_WAY_CH2_15 MC_RIR_LIMIT_CH2_0 MC_RIR_WAY_CH2_16 MC_RIR_LIMIT_CH2_1 MC_RIR_WAY_CH2_17 MC_RIR_LIMIT_CH2_2 MC_RIR_WAY_CH2_18 MC_RIR_LIMIT_CH2_3 MC_RIR_WAY_CH2_19 MC_RIR_LIMIT_CH2_4...

  • Page 35: Device 6, Function 3: Integrated Memory Controller Channel

    Register Description Table 2-19. Device 6, Function 3: Integrated Memory Controller Channel 2 Thermal Control Registers MC_COOLING_COEF2 PCISTS PCICMD MC_CLOSED_LOOP2 MC_THROTTLE_OFFSET2 MC_RANK_VIRTUAL_TEMP2 MC_DDR_THERM_COMMAND2 MC_DDR_THERM_STATUS2 SVID MC_THERMAL_CONTROL2 MC_THERMAL_STATUS2 MC_THERMAL_DEFEATURE2 MC_THERMAL_PARAMS_A2 MC_THERMAL_PARAMS_B2 Datasheet...

  • Page 36: Pci Standard Registers

    Value Vendor Identification Number 15:0 8086h The value assigned to Intel. 2.5.2 DID - Device Identification Register This 16-bit register combined with the Vendor Identification register uniquely identifies the Function within the processor. Writes to this register have no effect. See Table 2-1 for the DID of each processor function.

  • Page 37: Rid - Revision Identification Register

    Value Revision Identification Number Refer to the ® ® Intel Core™ i7 Processor Extreme Edition and Intel Core™ i7 for the value of the Revision ID Register. Processor Specification Update 2.5.4 CCR - Class Code Register This register contains the Class Code for the device. Writes to this register have no effect.

  • Page 38: Hdr - Header Type Register

    Function: 0-2, 4 Offset: 2Ch, 2Eh Device: Function: Offset: 2Ch, 2Eh Access as a Dword Reset Type Description Value Subsystem Identification Number 31:16 8086h The default value specifies Intel Vendor Identification Number 15:0 8086h The default value specifies Intel. Datasheet...

  • Page 39: Pcicmd - Command Register

    Register Description 2.5.7 PCICMD - Command Register This register defines the PCI 3.0 compatible command register values applicable to PCI Express space. Device: Function: Offset: Device: Function: 0-1, 4-5 Offset: Device: Function: 0-2, 4 Offset: Device: Function: Offset: Reset Type Description Value 15:11...

  • Page 40: Pcists - Pci Status Register

    Register Description 2.5.8 PCISTS - PCI Status Register The PCI Status register is a 16-bit status register that reports the occurrence of various error events on this device's PCI interface. Device: Function: Offset: Device: Function: 0-1, 4-5 Offset: Device: Function: 0-2, 4 Offset: Device:...

  • Page 41: Sad - System Address Decoder Registers

    Register Description Device: Function: Offset: Device: Function: 0-1, 4-5 Offset: Device: Function: 0-2, 4 Offset: Device: Function: Offset: Reset Type Description Value Capability List (CLIST) This bit is hardwired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities. A list of new capabilities is accessed via registers CAPPTR at the configuration address offset 34h from the start of the PCI configuration space header of this function.
  • Page 42 Register Description Device: Function: 1 Offset: Access as a Dword Reset Type Description Value PAM3_LOENABLE. 0D0000h-0D3FFFh Attribute (LOENABLE). This field controls the steering of read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh. 00 = DRAM Disabled: All accesses are directed to ESI. 25:24 01 = Read Only: All reads are sent to DRAM.

  • Page 43: Sad_Pam456

    Register Description 2.6.2 SAD_PAM456 Register for legacy device 0, function 0 94h-97h address space. Device: Function: 1 Offset: Access as a Dword Reset Type Description Value 21:20 PAM6_HIENABLE. 0EC000h-0EFFFFh Attribute (HIENABLE). This field controls the steering of read and write cycles that address the BIOS area from 0EC000h to 0EFFFFh.

  • Page 44: Sad_Hen

    Register Description 2.6.3 SAD_HEN Register for legacy Hole Enable. Device: Function: 1 Offset: Access as a Dword Reset Type Description Value HEN: Hole Enable This field enables a memory hole in DRAM space. The DRAM that lies "behind" this space is not remapped. 0 = No Memory hole.

  • Page 45: Sad_Pciexbar

    Register Description 2.6.5 SAD_PCIEXBAR Global register for PCIEXBAR address space. Device: Function: 1 Offset: Access as a Qword Reset Type Description Value ADDRESS. 39:20 Base address of PCIEXBAR. Must be naturally aligned to size; low order bits are ignored. SIZE. Size of the PCIEXBAR address space.

  • Page 46: Sad_Interleave_List_0, Sad_Interleave_List_1

    Register Description Device: Function: 1 Offset: 80h, 84h, 88h, 8Ch, 90h, 94h, 98h, 9Ch Access as a Dword LIMIT DRAM rule top limit address. Must be strictly greater than previous rule, even if 19:6 this rule is disabled, unless this rule and all following rules are disabled. Lower limit is the previous rule (or 0 if it is first rule).

  • Page 47: Intel Qpi Link Registers

    Register Description Intel QPI Link Registers 2.7.1 QPI_QPILCL_L0, QPI_QPILCL_L1 This register provides Intel QPI Link Control. Device: Function: 0, 4 Offset: Access as a Dword Reset Type Description Value L1_MASTER Indicates that this end of the link is the L1 master. This link transmitter bit is an L1 power state master and can initiate an L1 power state transition.
  • Page 48 Register Description Device: Function: 0 Offset: Access as a Dword CHANNEL0_ACTIVE When set, indicate MC channel 0 is active. This bit is controlled (set/reset) by software only. This bit is required to be set for any active channel when INIT_DONE is set by software. Channel 0 AND Channel 1 active must both be set for a lockstep or mirrored pair.

  • Page 49: Mc_Status

    Register Description 2.8.2 MC_STATUS This register is the MC primary status register. Device: Function: 0 Offset: Access as a Dword Reset Type Description Value ECC_ENABLED. ECC is enabled. CHANNEL2_DISABLED Channel 2 is disabled. This can be factory configured or if Init done is written without the channel_active being set.

  • Page 50: Mc_Smi_Spare_Dimm_Error_Status

    Register Description 2.8.3 MC_SMI_SPARE_DIMM_ERROR_STATUS SMI sparing DIMM error threshold overflow status register. This bit is set when the per- DIMM error counter exceeds the specified threshold. The bit is reset by BIOS. Device: Function: 0 Offset: Access as a Dword Reset Type Description...

  • Page 51: Mc_Smi_Spare_Cntrl

    Register Description 2.8.4 MC_SMI_SPARE_CNTRL System Management Interrupt and Spare control register. Device: Function: 0 Offset: Access as a Dword Reset Type Description Value INTERRUPT_SELECT_NMI 1 = Enable NMI signaling. 0 = Disable NMI signaling. If both NMI and SMI enable bits are set, then only SMI is sent. INTERRUPT_SELECT_SMI 1 = Enable SMI signaling.

  • Page 52: Mc_Channel_Mapper

    Register Description 2.8.6 MC_CHANNEL_MAPPER Channel mapping register. The sequence of operations to update this register is: Read MC_Channel_Mapper register Compare data read to data to be written. If different, then write. Poll MC_Channel_Mapper register until the data read matches data written. Device: Function: 0 Offset:...

  • Page 53: Mc_Max_Dod

    Register Description 2.8.7 MC_MAX_DOD This register defines the MAX number of DIMMS, RANKS, BANKS, ROWS, COLS among all DIMMS populating the three channels. The Memory Init logic uses this register to cycle through all the memory addresses writing all 0's to initialize all locations. This register is also used for scrubbing and sparing and must always be programmed if any DODs are programmed.

  • Page 54: Mc_Rd_Crdt_Init

    Register Description 2.8.8 MC_RD_CRDT_INIT These registers contain the initial read credits available for issuing memory reads. TAD read credit counters are loaded with the corresponding values at reset and anytime this register is written. BIOS must initialize this register with appropriate values depending on the level of Isoch support in the platform.

  • Page 55: Mc_Crdt_Wr_Thld

    Register Description 2.8.9 MC_CRDT_WR_THLD This is the Memory Controller Write Credit Thresholds register. A Write threshold is defined as the number of credits reserved for this priority (or higher) request. It is required that High threshold be greater than or equal to Crit threshold, and that both be lower than the total Write Credit init value.

  • Page 56: Mc_Scrubaddr_Hi

    Register Description 2.8.11 MC_SCRUBADDR_HI This register pair contains part of the address of the last patrol scrub request issued. When running memtest, the failing address is logged in this register on memtest errors. Software can write the next address into this register. Scrubbing must be disabled to reliably read and write this register.

  • Page 57: Tad - Target Address Decoder Registers

    Register Description TAD – Target Address Decoder Registers 2.9.1 TAD_DRAM_RULE_0, TAD_DRAM_RULE_1 TAD_DRAM_RULE_2, TAD_DRAM_RULE_3 TAD_DRAM_RULE_4, TAD_DRAM_RULE_5 TAD_DRAM_RULE_6, TAD_DRAM_RULE_7 TAD DRAM rules. Address map for channel determination within a package. All addresses sent to this HOME agent must hit a valid enabled DRAM_RULE. No error will be generated if they do not hit a valid location and memory aliasing will happen.

  • Page 58: Tad_Interleave_List_0, Tad_Interleave_List_1

    Register Description 2.9.2 TAD_INTERLEAVE_LIST_0, TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_2, TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_4, TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_6, TAD_INTERLEAVE_LIST_7 TAD DRAM package assignments. When the corresponding DRAM_RULE hits, a 3-bit number (determined by mode) is used to index into the Interleave_List Branches to determine which channel the DRAM request belongs to. Device: Function: 1 Offset:...

  • Page 59: Integrated Memory Controller Channel Control Registers

    Register Description Device: Function: 1 Offset: C0h, C4h, C8h, CCh, D0h, D4h, D8h, DCh Access as a Dword Logical Channel2. Index 010 of the Interleave List. Bits determined from the matching TAD_DRAM_RULE mode. 00 = Logical channel 0 01 = Logical channel 1 10 = Logical channel 2 11 = Reserved Logical Channel1.

  • Page 60: Mc_Channel_0_Dimm_Init_Cmd

    Register Description 2.10.2 MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_1_DIMM_INIT_CMD MC_CHANNEL_2_DIMM_INIT_CMD Integrated Memory Controller DIMM initialization command register. This register is used to sequence the channel through the physical layer training required for DDR. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description...

  • Page 61: Mc_Channel_0_Dimm_Init_Params

    Register Description 2.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_1_DIMM_INIT_PARAMS MC_CHANNEL_2_DIMM_INIT_PARAMS Initialization sequence parameters are stored in this register. Each field is 2^n count. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description Value DIS_3T. When set, 3T mode will not be enabled as a part of the MRS write to the RDIMM.

  • Page 62: Mc_Channel_0_Dimm_Init_Status

    Register Description 2.10.4 MC_CHANNEL_0_DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS MC_CHANNEL_2_DIMM_INIT_STATUS The initialization state is stored in this register. This register is cleared on a new training command. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description Value RCOMP_CMPLT. When set, indicates that RCOMP command has complete. This bit is cleared by hardware on command issuance and set once the command is complete.

  • Page 63: Mc_Channel_0_Ddr3Cmd

    Register Description 2.10.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD MC_CHANNEL_2_DDR3CMD DDR3 Configuration Command. This register is used to issue commands to the DIMMs such as MRS commands. The register is used by setting one of the *_VALID bits along with the appropriate address and destination RANK. The command is then issued directly to the DIMM.

  • Page 64: Mc_Channel_0_Refresh_Throttle_Support

    Register Description 2.10.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT This register supports Self Refresh and Thermal Throttle functions. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description Value INC_ENTERPWRDWN_RATE. Powerdown rate will be increased during thermal throttling based on the following configurations.

  • Page 65: Mc_Channel_0_Mrs_Value_2

    Register Description 2.10.8 MC_CHANNEL_0_MRS_VALUE_2 MC_CHANNEL_1_MRS_VALUE_2 MC_CHANNEL_2_MRS_VALUE_2 The initial MRS register values for MR2. This register also contains the values used for RC0 and RC2 writes for registered DIMMs. These values are used during the automated training sequence when MRS writes or registered DIMM RC writes are used. The RC fields do not need to be programmed if the address inversion and 3T/1T transitions are disabled.

  • Page 66: Mc_Channel_0_Rank_Timing_A Mc_Channel_1_Rank_Timing_A Mc_Channel_2_Rank_Timing_A

    Register Description 2.10.10 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A MC_CHANNEL_2_RANK_TIMING_A This register contains parameters that specify the rank timing used. All parameters are in DCLK. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description Value tddWrTRd. Minimum delay between a write followed by a read to different DIMMs. 000 = 1 001 = 2 010 = 3...
  • Page 67 Register Description Device: 4, 5, 6 Function: 0 Offset: Access as a Dword tddRdTWr. Minimum delay between Read followed by a Write to different DIMMs. 0000 = 2 0001 = 3 0010 = 4 0011 = 5 0100 = 6 18:15 0101 = 7 0110 = 8...
  • Page 68 Register Description Device: 4, 5, 6 Function: 0 Offset: Access as a Dword tddRdTRd. Minimum delay between reads to different DIMMs. 000 = 2 001 = 3 010 = 4 011 = 5 100 = 6 101 = 7 110 = 8 111 = 9 tdrRdTRd.

  • Page 69: Mc_Channel_0_Rank_Timing_B Mc_Channel_1_Rank_Timing_B Mc_Channel_2_Rank_Timing_B

    Register Description 2.10.11 MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_1_RANK_TIMING_B MC_CHANNEL_2_RANK_TIMING_B This register contains parameters that specify the rank timing used. All parameters are in DCLK. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description Value B2B_CAS_DELAY. Controls the delay between CAS commands in DCLKS. The minimum spacing is 4 DCLKS.

  • Page 70: Mc_Channel_0_Bank_Timing

    Register Description 2.10.12 MC_CHANNEL_0_BANK_TIMING MC_CHANNEL_1_BANK_TIMING MC_CHANNEL_2_BANK_TIMING This register contains parameters that specify the bank timing parameters. These values are in DCLK. The values in these registers are encoded where noted. All of these values apply to commands to the same rank only. Device: 4, 5, 6 Function: 0...

  • Page 71: Mc_Channel_0_Cke_Timing Mc_Channel_1_Cke_Timing

    Register Description 2.10.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_2_CKE_TIMING This register contains parameters that specify the CKE timings. All units are in DCLK. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description Value tRANKIDLE. Rank will go into powerdown after it has been idle for the specified number of dclks.

  • Page 72: Mc_Channel_0_Rcomp_Params

    Register Description 2.10.16 MC_CHANNEL_0_RCOMP_PARAMS MC_CHANNEL_1_RCOMP_PARAMS MC_CHANNEL_2_RCOMP_PARAMS This register contains parameters that specify Rcomp timings. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description Value RCOMP_EN. Enable Rcomp. When set, the Integrated Memory Controller will do the programmed blocking of requests and send indications.

  • Page 73: Mc_Channel_0_Odt_Params2

    Register Description 2.10.18 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_1_ODT_PARAMS2 MC_CHANNEL_2_ODT_PARAMS2 This register contains parameters that specify Forcing ODT on Specific ranks. This register is used in debug only and not during normal operation. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description...

  • Page 74: Mc_Channel_0_Odt_Matrix_Rank_4_7_Rd Mc_Channel_1_Odt_Matrix_Rank_4_7_Rd Mc_Channel_2_Odt_Matrix_Rank_4_7_Rd

    Register Description 2.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD This register contains the ODT activation matrix for RANKS 4 to 7 for Reads. Device: 4, 5, 6 Function:)0 Offset: Access as a Dword Reset Type Description Value 31:24 ODT_RD7. Bit patterns driven out onto ODT pins when Rank7 is read. 23:16 ODT_RD6.

  • Page 75: Mc_Channel_0_Waq_Params

    Register Description 2.10.23 MC_CHANNEL_0_WAQ_PARAMS MC_CHANNEL_1_WAQ_PARAMS MC_CHANNEL_2_WAQ_PARAMS This register contains parameters that specify settings for the Write Address Queue. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description Value PRECASWRTHRESHOLD. 29:25 Threshold above which Medium-Low Priority reads cannot PRE-CAS write requests.

  • Page 76: Mc_Channel_0_Scheduler_Params

    Register Description 2.10.24 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS MC_CHANNEL_2_SCHEDULER_PARAMS These are the parameters used to control parameters within the scheduler. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description Value CS_FOR_CKE_TRANSITION. Specifies if chip select is to be asserted when CKE transitions with PowerDown entry/exit and SelfRefresh exit.

  • Page 77: Mc_Channel_0_Tx_Bg_Settings

    Register Description 2.10.26 MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_1_TX_BG_SETTINGS MC_CHANNEL_2_TX_BG_SETTINGS These are the parameters used to set the Start Scheduler for TX clock crossing. This is used to send commands to the DIMMs. The NATIVE RATIO is UCLK multiplier of BCLK = U ALIEN RATION is DCLK multiplier of BCLK = D PIPE DEPTH = 8 UCLK (design dependent variable) MIN SEP DELAY = 670ps (design dependent variable, Internally this is logic delay of FIFO + clock skew between U and D)

  • Page 78: Mc_Channel_0_Ew_Bgf_Settings

    Register Description 2.10.28 MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS MC_CHANNEL_2_EW_BGF_SETTINGS These are the parameters used to set the early warning RX clock crossing BGF. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description Value 15:8 ALIENRATIO. Dclk to Bclk ratio. Early warning Alien Ratio setting. 2.10.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS...

  • Page 79: Mc_Channel_0_Pagetable_Params1

    Register Description 2.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1 MC_CHANNEL_1_PAGETABLE_PARAMS1 MC_CHANNEL_2_PAGETABLE_PARAMS1 These are the parameters used to control parameters for page closing policies.. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description Value 15:8 REQUESTCOUNTER. This field is the upper 8 MSBs of a 12-bit counter. This counter determines the window over which the page close policy is evaluated.

  • Page 80: Mc_Tx_Bg_Cmd_Data_Ratio_Settings_Ch2

    Register Description 2.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH2 Channel Bubble Generator ratios for CMD and DATA. Device: 4, 5, 6 Function: 0 Offset: Access as a Dword Reset Type Description Value 15:8 ALIENRATIO. DCLK to BCLK ratio. NATIVERATIO. UCLK to BCLK ratio. 2.10.34 MC_TX_BG_CMD_OFFSET_SETTINGS_CH0 MC_TX_BG_CMD_OFFSET_SETTINGS_CH1...

  • Page 81: Mc_Channel_0_Addr_Match

    Register Description 2.10.36 MC_CHANNEL_0_ADDR_MATCH MC_CHANNEL_1_ADDR_MATCH MC_CHANNEL_2_ADDR_MATCH This register specifies the intended address or address range where ECC errors will be injected. It can be set to match memory address on a per channel basis. The address fields can be masked in the Mask bits. Any mask bits set to 1 will always match. To match all addresses, all of the mask bits can be set to 1.

  • Page 82: Mc_Channel_0_Ecc_Error_Mask

    Register Description 2.10.37 MC_CHANNEL_0_ECC_ERROR_MASK MC_CHANNEL_1_ECC_ERROR_MASK MC_CHANNEL_2_ECC_ERROR_MASK This register contains mask bits for the memory controller and specifies at which ECC bit(s) the error injection should occur. Any bits set to a 1 will flip the corresponding ECC bit. Correctable errors can be injected by flipping 1 bit or the bits within a symbol pair (2 consecutive aligned 8-bit pairs - i.e.
  • Page 83 Register Description 2.10.39 Error Injection Implementation The usage model is to program the MC_CHANNEL_X_ADDR_MATCH and MC_CHANNEL_X_ECC_ERROR_MASK registers before writing the command in MC_CHANNEL_X_ECC_ERROR_INJECT register. When writing the MC_CHANNEL_X_ECC_ERROR_INJECT register, the REPEAT_EN and MASK_HALF_CACHELINE bits need to be set to the desired values. To turn off the feature, write 0 to the MC_CHANNEL_X_ECC_ERROR_INJECT register.
  • Page 84 Register Description 2.11 Integrated Memory Controller Channel Address Registers 2.11.1 MC_DOD_CH0_0, MC_DOD_CH0_1, MC_DOD_CH0_2 Channel 0 DIMM Organization Descriptor Register. Device: Function: 1 Offset: 48h, 4Ch, 50h Access as a Dword Reset Type Description Value RANKOFFSET. Rank Offset for calculating RANK. This corresponds to the first logical rank on the DIMM.
  • Page 85 Register Description 2.11.2 MC_DOD_CH1_0, MC_DOD_CH1_1, MC_DOD_CH1_2 Channel 1 DIMM Organization Descriptor Register. Device: Function: 1 Offset: 48h, 4Ch, 50h Access as a Dword Reset Type Description Value RANKOFFSET. Rank Offset for calculating RANK. This field corresponds to the first logical rank on the DIMM. The rank offset is always programmed to 0 for the DIMM 0 DOD registers.
  • Page 86 Register Description 2.11.3 MC_DOD_CH2_0, MC_DOD_CH2_1, MC_DOD_CH2_2 Channel 2 DIMM Organization Descriptor Register. Device: Function: 1 Offset: 48h, 4Ch, 50h Access as a Dword Reset Type Description Value 12:10 RANKOFFSET. Rank Offset for calculating RANK. This field corresponds to the first logical rank on the DIMM. The rank offset is always programmed to 0 for the DIMM 0 DOD registers.
  • Page 87 Register Description 2.11.4 MC_SAG_CH0_0, MC_SAG_CH0_1, MC_SAG_CH0_2 MC_SAG_CH0_3, MC_SAG_CH0_4, MC_SAG_CH0_5 MC_SAG_CH0_6, MC_SAG_CH0_7, MC_SAG_CH1_0 MC_SAG_CH1_1, MC_SAG_CH1_2, MC_SAG_CH1_3 MC_SAG_CH1_4, MC_SAG_CH1_5, MC_SAG_CH1_6 MC_SAG_CH1_7, MC_SAG_CH2_0, MC_SAG_CH2_1 MC_SAG_CH2_2, MC_SAG_CH2_3, MC_SAG_CH2_4 MC_SAG_CH2_5, MC_SAG_CH2_6, MC_SAG_CH2_7 Channel Segment Address Registers. For each of the 8 interleave ranges, they specify the offset between the System Address and the Memory Address and the System Address bits used for level 1 interleave, which should not be translated to Memory Address bits.
  • Page 88 Register Description 2.12 Integrated Memory Controller Channel Rank Registers 2.12.1 MC_RIR_LIMIT_CH0_0, MC_RIR_LIMIT_CH0_1 MC_RIR_LIMIT_CH0_2, MC_RIR_LIMIT_CH0_3 MC_RIR_LIMIT_CH0_4, MC_RIR_LIMIT_CH0_5 MC_RIR_LIMIT_CH0_6, MC_RIR_LIMIT_CH0_7 MC_RIR_LIMIT_CH1_0, MC_RIR_LIMIT_CH1_1 MC_RIR_LIMIT_CH1_2, MC_RIR_LIMIT_CH1_3 MC_RIR_LIMIT_CH1_4, MC_RIR_LIMIT_CH1_5 MC_RIR_LIMIT_CH1_6, MC_RIR_LIMIT_CH1_7 MC_RIR_LIMIT_CH2_0, MC_RIR_LIMIT_CH2_1 MC_RIR_LIMIT_CH2_2, MC_RIR_LIMIT_CH2_3 MC_RIR_LIMIT_CH2_4, MC_RIR_LIMIT_CH2_5 MC_RIR_LIMIT_CH2_6, MC_RIR_LIMIT_CH2_7 Channel Rank Limit Range Registers. Device: Function: 2 Offset: 40h, 44h, 48h, 4Ch, 50h, 54h, 58h, 5Ch...
  • Page 89 Register Description 2.12.2 MC_RIR_WAY_CH0_0, MC_RIR_WAY_CH0_1 MC_RIR_WAY_CH0_2, MC_RIR_WAY_CH0_3 MC_RIR_WAY_CH0_4, MC_RIR_WAY_CH0_5 MC_RIR_WAY_CH0_6, MC_RIR_WAY_CH0_7 MC_RIR_WAY_CH0_8, MC_RIR_WAY_CH0_9 MC_RIR_WAY_CH0_10, MC_RIR_WAY_CH0_11 MC_RIR_WAY_CH0_12, MC_RIR_WAY_CH0_13 MC_RIR_WAY_CH0_14, MC_RIR_WAY_CH0_15 MC_RIR_WAY_CH0_16, MC_RIR_WAY_CH0_17 MC_RIR_WAY_CH0_18, MC_RIR_WAY_CH0_19 MC_RIR_WAY_CH0_20, MC_RIR_WAY_CH0_21 MC_RIR_WAY_CH0_22, MC_RIR_WAY_CH0_23 MC_RIR_WAY_CH0_24, MC_RIR_WAY_CH0_25 MC_RIR_WAY_CH0_26, MC_RIR_WAY_CH0_27 MC_RIR_WAY_CH0_28, MC_RIR_WAY_CH0_29 MC_RIR_WAY_CH0_30, MC_RIR_WAY_CH0_31 Channel Rank Interleave Way Range Registers. These registers allow the user to define the ranks and offsets that apply to the ranges defined by the LIMIT in the MC_RIR_LIMIT_CH registers.
  • Page 90 Register Description 2.12.3 MC_RIR_WAY_CH1_0, MC_RIR_WAY_CH1_1 MC_RIR_WAY_CH1_2, MC_RIR_WAY_CH1_3 MC_RIR_WAY_CH1_4, MC_RIR_WAY_CH1_5 MC_RIR_WAY_CH1_6, MC_RIR_WAY_CH1_7 MC_RIR_WAY_CH1_8, MC_RIR_WAY_CH1_9 MC_RIR_WAY_CH1_10, MC_RIR_WAY_CH1_11 MC_RIR_WAY_CH1_12, MC_RIR_WAY_CH1_13 MC_RIR_WAY_CH1_14, MC_RIR_WAY_CH1_15 MC_RIR_WAY_CH1_16, MC_RIR_WAY_CH1_17 MC_RIR_WAY_CH1_18, MC_RIR_WAY_CH1_19 MC_RIR_WAY_CH1_20, MC_RIR_WAY_CH1_21 MC_RIR_WAY_CH1_22, MC_RIR_WAY_CH1_23 MC_RIR_WAY_CH1_24, MC_RIR_WAY_CH1_25 MC_RIR_WAY_CH1_26, MC_RIR_WAY_CH1_27 MC_RIR_WAY_CH1_28, MC_RIR_WAY_CH1_29 MC_RIR_WAY_CH1_30, MC_RIR_WAY_CH1_31 Channel Rank Interleave Way Range Registers. These registers allow the user to define the ranks and offsets that apply to the ranges defined by the LIMIT in the MC_RIR_LIMIT_CH registers.
  • Page 91 Register Description 2.12.4 MC_RIR_WAY_CH2_0, MC_RIR_WAY_CH2_1 MC_RIR_WAY_CH2_2, MC_RIR_WAY_CH2_3 MC_RIR_WAY_CH2_4, MC_RIR_WAY_CH2_5 MC_RIR_WAY_CH2_6, MC_RIR_WAY_CH2_7 MC_RIR_WAY_CH2_8, MC_RIR_WAY_CH2_9 MC_RIR_WAY_CH2_10, MC_RIR_WAY_CH2_11 MC_RIR_WAY_CH2_12, MC_RIR_WAY_CH2_13 MC_RIR_WAY_CH2_14, MC_RIR_WAY_CH2_15 MC_RIR_WAY_CH2_16, MC_RIR_WAY_CH2_17 MC_RIR_WAY_CH2_18, MC_RIR_WAY_CH2_19 MC_RIR_WAY_CH2_20, MC_RIR_WAY_CH2_21 MC_RIR_WAY_CH2_22, MC_RIR_WAY_CH2_23 MC_RIR_WAY_CH2_24, MC_RIR_WAY_CH2_25 MC_RIR_WAY_CH2_26, MC_RIR_WAY_CH2_27 MC_RIR_WAY_CH2_28, MC_RIR_WAY_CH2_29 MC_RIR_WAY_CH2_30, MC_RIR_WAY_CH2_31 Channel Rank Interleave Way Range Registers. These registers allow the user to define the ranks and offsets that apply to the ranges defined by the LIMIT in the MC_RIR_LIMIT_CH registers.
  • Page 92 Register Description 2.13 Memory Thermal Control 2.13.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL1 MC_THERMAL_CONTROL2 Controls for the Integrated Memory Controller thermal throttle logic for each channel. Device: 4, 5, 6 Function: 3 Offset: Access as a Dword Reset Type Description Value APPLY_SAFE. Enable the application of safe values while MC_THERMAL_PARAMS_B.SAFE_INTERVAL is exceeded.
  • Page 93 Register Description 2.13.3 MC_THERMAL_DEFEATURE0 MC_THERMAL_DEFEATURE1 MC_THERMAL_DEFEATURE2 Thermal Throttle defeature register for each channel. Device: 4, 5, 6 Function: 3 Offset: Access as a Dword Reset Type Description Value THERM_REG_LOCK. RW1S When set, no further modification of all thermal throttle registers are allowed. This bit must be set to the same value for all channels.
  • Page 94 Register Description 2.13.5 MC_THERMAL_PARAMS_B0 MC_THERMAL_PARAMS_B1 MC_THERMAL_PARAMS_B2 Parameters used by the thermal throttling logic. Device: 4, 5, 6 Function: 3 Offset: Access as a Dword Reset Type Description Value SAFE_INTERVAL. Safe values for cooling coefficient and duty cycle will be applied while the SAFE_INTERVAL is exceeded.
  • Page 95 Register Description 2.13.7 MC_CLOSED_LOOP0 MC_CLOSED_LOOP1 MC_CLOSED_LOOP2 This register controls the closed loop thermal response of the DRAM thermal throttle logic. It supports immediate thermal throttle and 2X refresh. In addition, the register is used to configure the throttling duty cycle. Device: 4, 5, 6 Function: 3...
  • Page 96 Register Description 2.13.9 MC_RANK_VIRTUAL_TEMP0 MC_RANK_VIRTUAL_TEMP1 MC_RANK_VIRTUAL_TEMP2 This register contains the 8 most significant bits [37:30] of the virtual temperature of each rank. The difference between the virtual temperature and the sensor temperature can be used to determine how fast fan speed should be increased. The value stored is right shifted one bit to the right with respect to the corresponding MC_Throttle_Offset register value.
  • Page 97 Register Description 2.13.11 MC_DDR_THERM_STATUS0 MC_DDR_THERM_STATUS1 MC_DDR_THERM_STATUS2 This register contains the status portion of the DDR_THERM# functionality as described in the processor datasheet (i.e., what is happening or has happened with respect to the pin). Device: 4, 5, 6 Function: 3 Offset: Access as a Dword Reset...
  • Page 98 Register Description 2.14.2 MC_DIMM_CLK_RATIO This register is for the Requested DIMM clock ratio (Qclk). This is the data rate going to the DIMM. The clock sent to the DIMM is 1/2 of QCLK rate. Device: Function: 4 Offset: Access as a Dword Reset Type Description...

This manual is also suitable for:

Core i7

Table of Contents