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10.1.1.3
Bit 2 - Timer Auto Reload Enable (TMRx.reload)
The TMRx.reload bit determines whether the timer runs continuously or in single-shot mode.
When TCRx = 0 and TMRx.enable = 1 and:
TMRx.reload = 1
The timer runs continuously. The processor:
1.
Automatically loads TCRx with the value in the Timer Reload Register (TRRx), when TCRx
value decrements to 0.
2.
Decrements TCRx until it equals 0 again.
Steps 1 and 2 repeat until software clears TMRx bits 1 or 2.
TMRx.reload = 0
The timer runs until the Timer Count Register = 0. TRRx has no effect on
the timer.
User software sets this bit. When TMRx.enable and TMRx.reload are set and TRRx does not equal
0, the timer continues to run in auto-reload mode, regardless of other processor activity.For
example, the timer runs while the processor is in Halt mode. Two events can stop the timer:
•
User software explicitly clearing either TMRx.enable or TMRx.reload.
•
Hardware or software reset. Refer to
The processor clears this bit upon hardware or software reset. Refer to
"INITIALIZATION" (pg.
12-2).
10.1.1.4
Bit 3 - Timer Register Supervisor Read/Write Control (TMRx.sup)
The TMRx.sup bit enables or disables user mode writes to the timer registers (TMRx, TCRx,
TRRx). Supervisor mode writes are allowed regardless of this bit's condition. Software can read
these registers from either mode.
When:
TMRx.sup = 1
The timer generates a TYPE
attempts a write to any of the timer registers; however, supervisor mode
writes are allowed.
TMRx.sup = 0
The timer registers can be written from either user or supervisor mode.
The processor clears TMRx.sup upon hardware or software reset. Refer to
"INITIALIZATION" (pg.
12-2).
section 12.2, "INITIALIZATION" (pg.
MISMATCH fault when a user mode task
.
TIMERS
12-2).
section 12.2,
10
section 12.2,
10-5
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