Table of Contents
Advertisement
CACHE AND ON-CHIP DATA RAM
4.3
BIG ENDIAN ACCESSES TO INTERNAL RAM AND DATA CACHE
The i960 Jx processor supports big-endian accesses to the internal data RAM and data cache. The
default byte order for data accesses is programmed in DLMCON.be as either little or big-endian.
The DLMCON.be controls the default byte-order for all internal (i.e., on-chip data RAM and data
cache) and external accesses. See
(pg. 13-8)
for more details.
4.4
INSTRUCTION CACHE
The i960 JT processor features a 16 Kbyte, 2-way set-associative instruction cache (I-cache). The
i960 JF and JD processors feature a 4-Kbyte, 2-way set-associative I-cache organized in lines of
four 32-bit words. The JA processor features a 2 Kbyte, 2-way set associative instruction cache.
The cache provides fast execution of cached code and loops of code and provides more bus
bandwidth for data operations in external memory. To optimize cache updates when branches or
interrupts are executed, each word in the line has a separate valid bit. When requested instructions
are found in the cache, the instruction fetch time is one cycle for up to four words. A mechanism to
load and lock critical code within a way of the cache is provided along with a mechanism to
disable the cache. The cache is managed through the
preferred and more versatile method for controlling the instruction cache on the i960 Jx processor.
Future i960 processors may not support
Cache misses cause the processor to issue a double-word or a quad-word fetch, based on the
location of the Instruction Pointer:
•
When the IP is at word 0 or word 1 of a 16-byte block, a four-word fetch is initiated.
•
When the IP is at word 2 or word 3 of a 16-byte block, a two-word fetch is initiated.
4.4.1
Enabling and Disabling the Instruction Cache
Enabling the instruction cache is controlled on reset or initialization by the instruction cache
configuration word in the Process Control Block (PRCB); see
bit 16 in the instruction cache configuration word is set, the instruction cache is disabled and all
instruction fetches are directed to external memory. Disabling the instruction cache is useful for
tracing execution in a software debug environment.
The instruction cache remains disabled until one of three operations is performed:
•
is issued with the enable instruction cache operation (preferred method)
icctl
•
sysctl
is issued with the configure-instruction-cache message type and cache configuration
mode other than disable cache (not the preferred method for i960 Jx processor).
•
The processor is reinitialized with a new value in the instruction cache configuration word
4-4
section 13.6, "Programming the Logical Memory Attributes"
or
icctl
sysctl
sysctl
instruction.
instruction. Using
is the
icctl
Figure 12-6 (pg.
12-17). When
Advertisement
Table of Contents
