Page 1 ® 2nd Generation Intel Core™ Processor Family Mobile Datasheet – Volume 1 ® Supporting Intel Core™ i7 Mobile Extreme Edition Processor Series and ® Intel Core™ i5 and i7 Mobile Processor Series This is Volume 1 of 2 January 2011...
Page 2 Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user.
Page 3: Table Of Contents
Platform Environment Control Interface (PECI) ........... 16 1.2.5 Processor Graphics ................. 16 1.2.6 Embedded DisplayPort* (eDP*) ..............17 ® ® 1.2.7 Intel Flexible Display Interface (Intel FDI) ..........17 Power Management Support ................17 1.3.1 Processor Core..................17 1.3.2 System ....................17 1.3.3 Memory Controller.................. 17 1.3.4...
Page 4 Display Planes ................34 2.4.2.2 Display Pipes ................35 2.4.2.3 Display Ports ................35 2.4.2.4 Embedded DisplayPort (eDP) ............35 2.4.3 Intel Flexible Display Interface..............35 2.4.4 Multi-Graphics Controller Multi-Monitor Support ..........36 Platform Environment Control Interface (PECI) ............36 Interface Clocking....................36 2.6.1 Internal Clocking Requirements ..............36 Technologies......................37 ®...
Page 5 Graphics Performance Modulation Technology(GPMT) ......59 4.6.3 Graphics Render C-State ................. 59 ® ® 4.6.4 Intel Smart 2D Display Technology (Intel S2DDT) ........59 ® 4.6.5 Intel Graphics Dynamic Frequency............60 4.6.6 Display Power Savings Technology 6.0 (DPST) ........... 60 4.6.7...
Page 6 6.13 Sense Pins ......................84 6.14 Ground and NCTF ....................85 6.15 Future Compatibility...................85 6.16 Processor Internal Pull Up/Pull Down ..............85 Electrical Specifications ...................87 Power and Ground Pins..................87 Decoupling Guidelines ..................87 7.2.1 Voltage Rail Decoupling ................87 7.2.2 PLL Power Supply ...................87 Voltage Identification (VID).................88 System Agent (SA) V VID ................92 Reserved or Unused Signals ................92...
Page 7  Figures ® 2nd Generation Intel Core™ Extreme Edition Processor Family Mobile Platform ........................ 12 ® Intel Flex Memory Technology Operation ..............25 PCI Express* Layering Diagram ................27 Packet Flow through the Layers ................28 PCI Express* Related Register Structures in the Processor..........29 PCIe Typical Operation 16 lanes Mapping ..............
Page 8 Memory Reference and Compensation ...............79 Reset and Miscellaneous Signals ................80 PCI Express* Graphics Interface Signals ..............80 Embedded Display Port Signals.................81 Intel® Flexible Display Interface................81 DMI - Processor to PCH Serial Interface ..............81 6-10 PLL Signals ......................82 6-11 TAP Signals......................82 6-12 Error and Thermal Protection..................83 6-13 Power Sequencing ....................83...
Page 9  7-15 PECI DC Electrical Limits ..................104 rPGA988B Processor Pin List by Pin Name..............112 BGA1224 Processor Ball List by Ball Name ............... 127 BGA1023 Processor Ball List by Ball Name ............... 146 DDR Data Swizzling Table – Channel A ..............170 DDR Data Swizzling Table –...
Page 10: Revision History
Revision History Revision Description Date Number • Initial Release January 2011 § § Datasheet, Volume 1...
Page 11: Introduction
® Note: Throughout this document, the 2nd Generation Intel Core™ processor family mobile may be referred to simply as “processor”. ®...
Page 12: 2Nd Generation Intel Platform
Introduction ® Figure 1-1. 2nd Generation Intel Core™ Extreme Edition Processor Family Mobile Platform PC I Express* 2.0 DDR3 1 x16 or 2x8 Discrete G raphics (PEG ) Processor PEC I Embedded Display Port DMI2 x4 Serial ATA Intel® Management...
Page 13: Processor Feature Details
• A 256-KB shared instruction/data second-level cache (L2) for each core • Up to 8-MB shared instruction/data third-level cache (L3), shared among all cores 1.1.1 Supported Technologies ® ® • Intel Virtualization Technology for Directed I/O (Intel VT-d) ® ® • Intel Virtualization Technology (Intel VT-x) ®...
Page 14: Pci Express
• Up to 32 simultaneous open pages, 16 per channel (assuming 4 Ranks of 8 Bank Devices) • Memory organizations — Single-channel modes ® — Dual-channel modes - Intel Flex Memory Technology: - Dual-channel symmetric (Interleaved) • Command launch modes of 1n/2n • On-Die Termination (ODT) •...
Page 15: Direct Media Interface (Dmi)
Introduction • PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space. •...
Page 16: Platform Environment Control Interface (Peci)
• The Processor Graphics contains a refresh of the sixth generation graphics core enabling substantial gains in performance and lower power consumption. Up to 12 EU Support. • Next Generation Intel Clear Video Technology HD support is a collection of video playback and enhancement features that improve the end user’s viewing experience.
Page 17: Embedded Displayport* (Edp*)
— FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization) • One Interrupt signal used for various interrupts from the PCH — FDI_INT signal shared by both Intel FDI Links • PCH supports end-to-end lane reversal across both links • Common 100-MHz reference clock Power Management Support 1.3.1...
Page 18: Processor Graphics Controller
1.3.6 Processor Graphics Controller • Rapid Memory Power Management RMPM – CxSR • Graphics Performance Modulation Technology (GPMT) • Intel Smart 2D Display Technology (Intel S2DDT) • Graphics Render C-State (RC6) ® • Intel Seamless Display Refresh Rate Switching with eDP port Thermal Management Support •...
Page 19 (Virtual Machine Manager or OS) ® Intel VT-d control, for enabling I/O device virtualization. Intel VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d. I/O Virtualization...
Page 20 Introduction Term Description Graphics core power supply. Processor core power supply. High Frequency I/O logic power supply CCIO PLL power supply CCPLL System Agent (memory controller, DMI, PCIe controllers, and display engine) CCSA power supply DDR3 power supply. Variable Length Decoding. Processor ground.
Page 21: Related Documents
Related Documents Refer to Table 1-2 for additional information. Table 1-2. Related Documents Document Document Number/ Location ® 2nd Generation Intel Core™ Processor Family Mobile Datasheet, Volume www.intel.com/Assets/PDF/datas heet/324803.pdf ® 2nd Generation Intel Core™ Processor Family Mobile Specification www.intel.com/Assets/PDF/specu pdate/324693.pdf Update ®...
Page 22 Introduction Datasheet, Volume 1...
Page 23: Interfaces
Interfaces Interfaces This chapter describes the interfaces supported by the processor. System Memory Interface 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3 protocols with two independent, 64-bit wide channels each accessing one DIMM. It supports a maximum of one unbuffered non-ECC DDR3 DIMM per-channel;...
Page 24: System Memory Timing Support
Dual-Channel Mode – Intel Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a symmetric and an asymmetric zone. The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached.
Page 25: Rules For Populating Memory Slots
Interfaces ® Figure 2-1. Intel Flex Memory Technology Operation T O M N o n in t e r le a v e d a c c e s s D u a l c h a n n e l...
Page 26: Fma)
® (Intel FMA) The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements. 2.1.5.1 Just-in-Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next.
Page 27: Pci Express* Interface
Interfaces PCI Express* Interface This section describes the PCI Express interface capabilities of the processor. See the PCI Express Base Specification for details of PCI Express. The processor has one PCI Express controller that can support one external x16 PCI Express Graphics Device.
Page 28: Transaction Layer
Interfaces packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device. Figure 2-3. Packet Flow through the Layers 2.2.1.1 Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer.
Page 29: Pci Express* Configuration Mechanism
Interfaces 2.2.2 PCI Express* Configuration Mechanism The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-4. PCI Express* Related Register Structures in the Processor PCI-PCI Bridge representing Compatible PEG0 Express root PCI Host Bridge Device Express ports Device (Device 1 and...
Page 30: Pci Express Lanes Connection
Interfaces 2.2.4 PCI Express Lanes Connection Figure 2-5 demonstrates the PCIe lanes mapping. Figure 2-5. PCIe Typical Operation 16 lanes Mapping Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7 Lane 8 Lane 9 Lane 10 Lane 11 Lane 12...
Page 31: Dmi Link Down
Interfaces 2.3.3 DMI Link Down The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to data link down, after the link was up, then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption. This link behavior is controlled by the PCH.
Page 32: 3D And Video Engines For Graphics Processing
Interfaces 2.4.1 3D and Video Engines for Graphics Processing The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive. All the cores are fully programmable, increasing the versatility of the 3D Engine. The Gen 6.0 3D engine provides the following performance and power-management enhancements: •...
Page 33: Video Engine
Interfaces 2.4.1.2.6 Windower/IZ (WIZ) Stage The WIZ unit performs an early depth test, which removes failing pixels and eliminates unnecessary processing overhead. The Windower uses the parameters provided by the SF unit in the object-specific rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of pixels.
Page 34: Processor Graphics Display
2.4.2 Processor Graphics Display The Processor Graphics controller display pipe can be broken down into three components: • Display Planes • Display Pipes ® • Embedded DisplayPort* and Intel Figure 2-7. Processor Display Block Diagram Display Display Port Pipe A...
Page 35: Display Pipes
FDI) is a proprietary link for carrying display ® traffic from the Processor Graphics controller to the PCH display I/Os. Intel supports two independent channels—one for pipe A and one for pipe B. • Each channel has four transmit (Tx) differential pairs used for transporting pixel and framing data from the display engine.
Page 36: Multi-Graphics Controller Multi-Monitor Support
Interfaces 2.4.4 Multi-Graphics Controller Multi-Monitor Support The processor supports simultaneous use of the Processor Graphics Controller (GT) and a x16 PCI Express Graphics (PEG) device. The processor supports a maximum of 2 displays connected to the PEG card in parallel with up to 2 displays connected to the processor and PCH.
Page 37: Technologies
OSs and applications without any special steps. • Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86 processors. • More reliable: Due to the hardware support, VMMs can now be smaller, less complex, and more efficient.
Page 38: Intel Vt-X Features
3.1.3 Intel VT-d Objectives The key Intel VT-d objectives are domain-based isolation and hardware-based virtualization. A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated. Virtualization allows for the creation of one or more partitions on a single system.
Page 39: Intel Vt-D Features
The following features are not supported by the processor with Intel VT-d: • No support for PCISIG endpoint caching (ATS) • No support for Intel VT-d read prefetching/snarfing (that is, translations within a cacheline are not stored in an internal buffer for reuse for subsequent translations).
Page 40: Intel Trusted Execution Technology (Intel Txt)
Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute.
Page 41: Intel Turbo Boost Technology
Therefore, most applications are consuming less than the TDP at the rated frequency. Intel Turbo Boost Technology takes advantage of the available TDP headroom and active cores are able to increase their operating frequency.
Page 42: Intel Advanced Vector Extensions (Avx)
Note: Processor utilization of turbo graphic frequencies requires that the Intel Graphics driver to be properly installed. Turbo graphic frequencies are not dependent on the operating system processor P-state requests and may turbo while the processor is in any processor P-states.
Page 43: Pclmulqdq Instruction
® Intel 64 Architecture x2APIC The x2APIC architecture extends the xAPIC architecture that provides a key mechanism for interrupt delivery. This extension is intended primarily to increase processor addressability.
Page 44 The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendibility for future Intel platform innovations. Note: Intel x2APIC technology may not be available on all processor SKUs. ® For more information, refer to the Intel 64 Architecture x2APIC Specification at http://www.intel.com/products/processor/manuals/...
Page 45: Power Management
Power Management Power Management This chapter provides information on the following power management topics: • ACPI States • Processor Core • Integrated Memory Controller (IMC) • PCI Express* • Direct Media Interface (DMI) • Processor Graphics Controller ACPI States Supported The ACPI states supported by the processor are described in this section.
Page 46: Integrated Memory Controller States
Power Management 4.1.3 Integrated Memory Controller States Table 4-3. Integrated Memory Controller States State Description Power up CKE asserted. Active mode. Pre-charge CKE de-asserted (not self-refresh) with all banks closed. Power-down Active Power- CKE de-asserted (not self-refresh) with minimum one bank active. Down Self-Refresh CKE de-asserted using device self-refresh.
Page 47: Interface State Combinations
Power Management 4.1.7 Interface State Combinations Table 4-7. G, S, and C State Combinations Processor Global (G) Sleep Processor Package System Clocks Description State (S) State State (C) State Full On Full On C1/C1E Auto-Halt Auto-Halt Deep Sleep Deep Sleep Deep Power- C6/C7 Deep Power-down...
Page 48: Processor Core Power Management
Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology: • Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. • Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores.
Page 49: Idle Power Management Breakdown Of The Processor Cores
Power Management Figure 4-1. Idle Power Management Breakdown of the Processor Cores Thread 0 Thread 1 Thread 0 Thread 1 Core 0 State Core 1 State Processor Package State Entry and exit of the C-States at the thread and core level are shown in Figure 4-2.
Page 50: Requesting Low-Power Idle States
Power Management Table 4-9. Coordination of Thread Power States at the Core Level Thread 1 Processor Core C-State Thread 0 Note: If enabled, the core C-state will be C1E if all cores have resolved a core C1 state or higher. 4.2.3 Requesting Low-Power Idle States The primary software interfaces for requesting low power idle states are through the...
Page 51: Core C-States
MWAIT(C1/C1E) instruction. A System Management Interrupt (SMI) handler returns execution to either Normal ® state or the C1/C1E state. See the Intel 64 and IA-32 Architecture Software Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads.
Page 52: C-State Auto-Demotion
Power Management 4.2.4.6 C-State Auto-Demotion In general, deeper C-states such as C6 or C7 have long latencies and have higher energy entry/exit costs. The resulting performance and energy penalties become significant when the entry/exit frequency of a deeper C-state is high. Therefore, incorrect or inefficient usage of deeper C-states have a negative impact on battery life idle.
Page 53: Package C0
Power Management Table 4-11 shows package C-state resolution for a dual-core processor. Figure 4-3 summarizes package C-state transitions. Table 4-11. Coordination of Core Power States at the Package Level Core 1 Package C-State Core 0 Note: If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher. Figure 4-3.
Page 54: Package C1/C1E
Power Management 4.2.5.2 Package C1/C1E No additional power reduction actions are taken in the package C1 state. However, if the C1E sub-state is enabled, the processor automatically transitions to the lowest supported core clock frequency, followed by a reduction in voltage. The package enters the C1 low power state when: •...
Page 55: Package C7 State
Power Management 4.2.5.5 Package C7 State The processor enters the package C7 low power state when all cores are in the C7 state and the L3 cache is completely flushed. The last core to enter the C7 state begins to shrink the L3 cache by N-ways until the entire L3 cache has been emptied.
Page 56: Dram Power Management And Initialization
Power Management 4.3.2 DRAM Power Management and Initialization The processor implements extensive support for power management on the SDRAM interface. There are four SDRAM operations associated with the Clock Enable (CKE) signals that the SDRAM controller supports. The processor drives four CKE pins to perform these operations.
Page 57: Initialization Role Of Cke
4.3.2.2 Conditional Self-Refresh Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into self-refresh in the package C3, C6, and C7 low-power states. RMPM functionality depends on the graphics/display state (relevant only when processor graphics is being used), as well as memory traffic patterns generated by other connected I/O devices.
Page 58: Dynamic Power-Down Operation
Power Management Table 4-12. Targeted Memory State Conditions Mode Memory State with Processor Graphics Memory State with External Graphics Dynamic memory rank power down based on Dynamic memory rank power down based on C0, C1, C1E idle conditions. idle conditions. If the Processor Graphics engine is idle and If there are no memory requests, then enter there are no pending display requests, then...
Page 59: Graphics Power Management
Technology(GPMT) ® Intel Graphics Power Modulation Technology (Intel GPMT) is a method for saving power in the graphics adapter while continuing to display and process data in the adapter. This method will switch the render frequency and/or render voltage dynamically between higher and lower power states supported on the platform based on render engine workload.
Page 60: Intel Graphics Dynamic Frequency
The sensor receives the changing ambient light conditions and sends the interrupts to the Intel Graphics driver. As per the change in Lux, (current ambient light illuminance), the new backlight setting can be adjusted through BLC (see section 11).
Page 61: Seamless Display Refresh Rate Switching Technology (Sdrrst)
(SDRRST) This is a mobile only supported power management feature. ® When a Local Flat Panel (LFP) supports multiple refresh rates, the Intel Display Refresh Rate Switching power conservation feature can be enabled. The higher refresh rate will be used when on plugged in power or when the end user has not selected/enabled this feature.
Page 62 Power Management Datasheet, Volume 1...
Page 63: Thermal Management
Thermal Management Thermal Management The thermal solution provides both the component-level and the system-level thermal management. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed so that the processor: •...
Page 64: Intel ® Turbo Boost Technology Power Control And Reporting
Circuitry (TCC) will protect the processor when properly enabled. Adaptive Thermal Monitor must be enabled for the processor to remain within specification. Illustration of Intel Turbo Boost Technology power control is shown in the following sections and figures. Multiple controls operate simultaneously allowing for customization for multiple system thermal and power limitations.
Page 65: Package Power Control
Thermal Management 5.2.2 Package Power Control The package power control allows for customization to implement optimal turbo within platform power delivery and package thermal solution limitations. Figure 5-1. Package Power Control Turbo Algorithm Response Time System Thermal Response Time 5.2.3 Power Plane Control The processor core and graphics core power plane controls allow for customization to implement optimal turbo within voltage regulator thermal limitations.
Page 66: Thermal And Power Specifications
5.4.1.2.1. Digital Thermal Sensor (DTS) based fan speed control is required to achieve optimal thermal performance. Intel recommends full cooling capability well before the DTS reading reaches Tj,Max. An example of this is Tj,Max – 10 ºC. The idle power specifications are not 100% tested. These power specifications are determined by the characterization at higher temperatures and extrapolating the values for the junction temperature indicated.
Page 67: Tdp Specifications
Thermal Management Table 5-1. TDP Specifications CPU Core Processor Graphics Thermal Design Segment State Units Notes Frequency Core frequency Power 2.5 GHz up to 650 MHz up to 3.5 GHz 1300 MHz Extreme 1, 2, 7 Edition (XE) 650 MHz up to 800 MHz 1300 MHz 2.2 GHz...
Page 68: Package Turbo Parameters
Thermal Management Table 5-3. Package Turbo Parameters (Sheet 1 of 2) Segment Symbol Package Turbo Parameter Units Notes Default Processor turbo long duration time window Turbo Time 10, 11, Parameter (POWER_LIMIT_1_TIME in (package) TURBO_POWER_LIMIT MSR 0610h bits [23:17]) 'Long duration' turbo power limit Extreme Edition Long P...
Page 69: Idle Power Specifications
Thermal Management Table 5-3. Package Turbo Parameters (Sheet 2 of 2) Segment Symbol Package Turbo Parameter Units Notes Default Processor turbo long duration time window Turbo Time Parameter 0.001 10,11,14 (POWER_LIMIT_1_TIME in (package) TURBO_POWER_LIMIT MSR 0610h bits [23:17]) 'Long duration' turbo power limit Ultra Low Long P 10,12,...
Page 70: Thermal Management Features
Thermal Management Thermal Management Features This section covers thermal management features for the processor. 5.4.1 Processor Package Thermal Features This section covers thermal management features for the entire processor complex (including the processor core, the graphics core, and integrated memory controller hub), and will be referred to as processor package, or by simply the package.
Page 71: Frequency And Voltage Ordering
The operating points are automatically calculated by the processor core itself and do not require the BIOS to program them as with previous generations of Intel processors. The processor core will scale the operating points such that: •...
Page 72: Digital Thermal Sensor
• It will be necessary to transition through multiple VID steps to reach the target operating voltage. • Each step is 5 mV for Intel MVP-7.0 compliant VRs. • The processor continues to execute instructions. However, the processor will halt instruction execution for frequency transitions.
Page 73: Prochot# Signal
When temperature is retrieved using PECI, it is the average of the highest DTS temperature in the package over a 256 ms time window. Intel recommends using the PECI reported temperature for platform thermal control that benefits from averaging, such as fan speed control.
Page 74 Thermal Management 5.4.1.3.1 Bi-Directional PROCHOT# By default, the PROCHOT# signal is defined as an output only. However, the signal may be configured as bi-directional. When configured as a bi-directional signal, PROCHOT# can be used for thermally protecting other platform components should they overheat as well.
Page 75: Processor Core Specific Thermal Features
PACKAGE_THERM_STATUS MSR 1B1h and also generates a thermal interrupt if ® enabled. For more details on the interrupt mechanism, refer to the Intel 64 and IA-32 Architectures Software Developer's Manuals.
Page 76: Memory Controller Specific Thermal Features
Platform Environment Control Interface (PECI) The Platform Environment Control Interface (PECI) is a one-wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices. The processor implements a PECI interface to allow communication of processor thermal information to other devices on the platform. The processor provides a digital thermal sensor (DTS) for fan speed control.
Page 77: Signal Description
Revision 1.0 DP specifications and the interface is AC coupled. The buffers are not 3.3-V tolerant. Intel Flexible Display interface signals. These signals are based on PCI Express* 2.0 Signaling Environment AC Specifications (2.7 GT/s), but are DC coupled. The buffers are not 3.3-V tolerant.
Page 78: System Memory Interface
Signal Description System Memory Interface Table 6-2. Memory Channel A Direction/ Signal Name Description Buffer Type Bank Select: These signals define which banks are selected within SA_BS[2:0] each SDRAM rank. DDR3 Write Enable Control Signal: This signal is used with SA_RAS# and SA_WE# SA_CAS# (along with SA_CS#) to define the SDRAM Commands.
Page 79: Memory Reference And Compensation
Signal Description Table 6-3. Memory Channel B Direction/ Signal Name Description Buffer Type Bank Select: These signals define which banks are selected within SB_BS[2:0] each SDRAM rank. DDR3 Write Enable Control Signal: This signal is used with SB_RAS# and SB_WE# SB_CAS# (along with SB_CS#) to define the SDRAM Commands.
Page 80: Reset And Miscellaneous Signals
Platform Reset pin driven by the PCH RESET# CMOS RESERVED: All signals that are RSVD and RSVD_NCTF must be left No Connect RSVD unconnected on the board. However, Intel recommends that all RSVD_TP Test Point RSVD_TP signals have using test points. Non-Critical RSVD_NCTF to Function DDR3 DRAM Reset: Reset signal from processor to DRAM devices.
Page 81: Embedded Displayport (Edp)
Diff Embedded DisplayPort Hot Plug Detect: eDP_HPD# Asynchronous CMOS Embedded DisplayPort Current Compensation eDP_COMPIO Embedded DisplayPort Current Compensation eDP_ICOMPO ® Intel Flexible Display Interface Signals ® Table 6-8. Intel Flexible Display Interface Direction/ Signal Name Description Buffer Type ®...
Page 82: Pll Signals
Signal Description PLL Signals Table 6-10. PLL Signals Direction/ Signal Name Description Buffer Type BCLK Differential bus clock input to the processor BCLK# Diff Clk DPLL_REF_CLK Embedded Display Port PLL Differential Clock In: 120 MHz. DPLL_REF_CLK# Diff Clk TAP Signals Table 6-11.
Page 83: Error And Thermal Protection
Signal Description 6.10 Error and Thermal Protection Table 6-12. Error and Thermal Protection Direction/ Signal Name Description Buffer Type Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors or other unrecoverable internal errors.
Page 84: Processor Power Signals
Signal Description 6.12 Processor Power Signals Table 6-14. Processor Power Signals Direction/ Signal Name Description Buffer Type Processor core power rail VCCIO Processor power for I/O VDDQ Processor I/O supply voltage for DDR3 VAXG Graphics core power supply. VCCPLL VCCPLL provides isolated power for internal processor PLLs VCCSA System Agent power supply VCCPQE...
Page 85: Ground And Nctf
Signal Description 6.14 Ground and NCTF Table 6-16. Ground and NCTF Direction/ Signal Name Description Buffer Type Processor ground node Non-Critical to Function: These pins are for package mechanical VSS_NCTF (BGA Only) reliability. Daisy Chain- These pins are for solder joint reliability and non-critical to DC_TEST_xx# function.
Page 86 Signal Description Datasheet, Volume 1...
Page 87: Electrical Specifications
Electrical Specifications Electrical Specifications Power and Ground Pins The processor has V and V (ground) inputs for CCIO DDQ, CCPLL, CCSA on-chip power distribution. All power pins must be connected to their respective processor power planes, while all VSS pins must be connected to the system ground plane.
Page 88: Voltage Identification (Vid)
Electrical Specifications Voltage Identification (VID) The VID specifications for the processor V and V are defined by the VR12/IMVP7 SVID Protocol. The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages. Table 7-1 specifies the voltage level corresponding to the eight bit VID value transmitted over serial VID.
Page 89: Imvp7 Voltage Identification Definition
Electrical Specifications Table 7-1. IMVP7 Voltage Identification Definition (Sheet 1 of 3) HEX V CC_MAX CC_MAX 0 0.00000 0.88500 1 0.25000 0.89000 2 0.25500 0.89500 3 0.26000 0.90000 4 0.26500 0.90500 5 0.27000 0.91000 6 0.27500 0.91500 7 0.28000 0.92000 8 0.28500 0.92500 9 0.29000...
Page 90 Electrical Specifications Table 7-1. IMVP7 Voltage Identification Definition (Sheet 2 of 3) HEX V CC_MAX CC_MAX A 0.45500 1.09500 B 0.46000 1.10000 C 0.46500 1.10500 D 0.47000 1.11000 E 0.47500 1.11500 F 0.48000 1.12000 0 0.48500 1.12500 1 0.49000 1.13000 2 0.49500 1.13500 3 0.50000...
Page 91 Electrical Specifications Table 7-1. IMVP7 Voltage Identification Definition (Sheet 3 of 3) HEX V CC_MAX CC_MAX 5 0.67000 1.31000 6 0.67500 1.31500 7 0.68000 1.32000 8 0.68500 1.32500 9 0.69000 1.33000 A 0.69500 1.33500 B 0.70000 1.34000 C 0.70500 1.34500 D 0.71000 1.35000 E 0.71500...
Page 92: Reserved Or Unused Signals
The Vcc is configured by the processor output pins VCCSA_VID[1:0]. ® VCCSA_VID[0] output default logic state is low for the 2nd Generation Intel Core™ processor family mobile; logic high is reserved for future compatibility. VCCSA_VID[1] output default logic state is low – will not change the SA voltage. Logic high will reduce the voltage.
Page 93: Signal Groups
Electrical Specifications Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 7-3. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals, have On- Die Termination (ODT) resistors.
Page 94 Differential eDP Bi-directional eDP_AUX, eDP_AUX# Asynchronous CMOS Single Ended eDP_HPD Input Single Ended Analog Input eDP_ICOMPO, eDP_COMPIO Differential DMI Input DMI_RX[3:0], DMI_RX#[3:0] Differential DMI Output DMI_TX[3:0], DMI_TX#[3:0] ® Intel FDI0_FSYNC, FDI1_FSYNC, FDI0_LSYNC, Single Ended CMOS Input FDI1_LSYNC Datasheet, Volume 1...
Page 95: Test Access Port (Tap) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage.
Page 96: Dc Specifications
JESD22-A103 (high temp) standards when applicable for volatile memory. Intel branded products are specified and certified to meet the following temperature and humidity limits that are given as an example only (Non-Operating Temperature Limit: -40 °C to 70 °C and Humidity: 50% to 90%, non-condensing with a maximum wet bulb of 28 °C.) Post board attach storage temperature limits...
Page 97: Voltage And Current Specifications
Electrical Specifications 7.9.1 Voltage and Current Specifications Table 7-5. Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications (Sheet 1 of 2) Symbol Parameter Segment Unit Note 1.35 SV-QC 1.35 VID Range for Highest 1, 2, 6, HFM_VID Frequency Mode (Includes SV-DC...
Page 98: Processor Uncore (Vccio) Supply Dc Voltage And Current Specifications
VID employed by the processor during a power or thermal management event (Intel Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States). The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-M...
Page 99: Memory Controller (Vddq) Supply Dc Voltage And Current Specifications
Electrical Specifications Table 7-7. Memory Controller (V ) Supply DC Voltage and Current Specifications Symbol Parameter Unit Note Processor I/O supply voltage for (DC+AC) — — DDR3 (DC + AC specification) Tolerance DC= ±3% AC= ±2% AC+DC= ±5% Max Current for V Rail —...
Page 100: Processor Graphics (Vaxg) Supply Dc Voltage And Current Specifications
VID employed by the processor during a power or thermal management event (Intel Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States). The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-M...
Page 101: Ddr3 Signal Group Dc Specifications
Electrical Specifications Table 7-11. DDR3 Signal Group DC Specifications Symbol Parameter Units Notes Input Low Voltage — — SM_VREF -0.1 2, 4, 11 Input High Voltage SM_VREF + 0.1 — — 3, 11 Input Low Voltage (SM_DRAMPWROK) — — *0.55 -0.1 Input High Voltage (SM_DRAMPWROK) *0.55 +0.1 —...
Page 102: Control Sideband And Tap Signal Group Dc Specifications
COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to V CCIO PEG_ICOMPO, PEG_ICOMPI, PEG_RCOMPO are the same resistor. Intel allows using 24.9 1% resistors. RMS value. Measured at Rx pins into a pair of 50-terminations into ground. Common mode peak voltage is defined by the expression: max{|(Vd+ - Vd-) –...
Page 103: Platform Environmental Control Interface (Peci) Dc Specifications
The idle state on the bus is near zero. Figure 7-1 demonstrates PECI design and connectivity, while the host/originator can be ® 3rd party PECI host, and one of the PECI client is a 2nd Generation Intel Core™ processor family mobile PECI device. Datasheet, Volume 1...
Page 104: Peci Dc Characteristics
Electrical Specifications Figure 7-1. Example for PECI Host-clients Connection 7.10.2 PECI DC Characteristics The PECI interface operates at a nominal voltage set by V The set of DC electrical CCIO specifications shown in Table 7-15 are used with devices normally operating from a interface supply.
Page 105: Input Device Hysteresis
Electrical Specifications 7.10.3 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 7-2 as a guide for input buffer design. Figure 7-2. Input Device Hysteresis Maximum V PECI High Range Minimum V...
Page 106 Electrical Specifications Datasheet, Volume 1...
Page 107: Processor Pin And Signal Information
Processor Pin and Signal Information Processor Pin and Signal Information Processor Pin As signments • Table 8-1, Table 8-2 Table 8-3 all pins ordered alphabetically for the rPGA988B BGA1224 and BGA1023 package respectively. • Figure 8-1, Figure 8-2, Figure 8-3 Figure 8-4 show the Top-Down view of the rPGA988B pinmap.
Page 108: Rpga988B (Socket-G2) Pinmap (Top View, Upper-Left Quadrant)
Processor Pin and Signal Information Figure 8-1. rPGA988B (Socket-G2) Pinmap (Top View, Upper-Left Quadrant) RSVD RSVD BPM#[ BPM#[ BPM#[ RSVD VAXG VAXG VAXG VAXG VAXG _NC TF _NC TF RSVD RSVD RESET BPM#[ BPM#[ BPM#[ BPM#[ TC K VAXG VAXG VAXG VAXG VAXG _NC TF...
Page 109: Rpga988B (Socket-G2) Pinmap (Top View, Upper-Right Quadrant)
 Processor Pin and Signal Information Figure 8-2. rPGA988B (Socket-G2) Pinmap (Top View, Upper-Right Quadrant) SB_D SB_D SB_D SB_D SB_D SB_D SB_D SB_D RSVD RSVD VAXG Q[63] Q[59] Q[60] Q[56] Q[51] Q[50] Q[43] Q[42] _NC TF _NC TF SA_D SB_D SB_D SA_D SB_D...
Page 110: Rpga988B (Socket-G2) Pinmap (Top View, Lower-Left Quadrant)
Processor Pin and Signal Information Figure 8-3. rPGA988B (Socket-G2) Pinmap (Top View, Lower-Left Quadrant) VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C...
Page 111: Rpga988B (Socket-G2) Pinmap (Top View, Lower-Right Quadrant)
 Processor Pin and Signal Information Figure 8-4. rPGA988B (Socket-G2) Pinmap (Top View, Lower-Right Quadrant) SM_D SA_C SA_C SA_M SA_BS SA_M SA_M SA_M SA_M SA_M RAMP KE[1] KE[0] A[15] A[14] A[11] A[4] A[5] A[8] WROK VC C I VDDQ VDDQ VDDQ RSVD RSVD...
Page 112: Rpga988B Processor Pin List By Pin Name
Processor Pin and Signal Information Table 8-1. rPGA988B Processor Pin Table 8-1. rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin # Buffer Type Pin Name Pin # Buffer Type BCLK Diff Clk DMI_TX[3] BCLK# Diff Clk DPLL_REF_CLK Diff Clk...
Page 113  Processor Pin and Signal Information Table 8-1. rPGA988B Processor Pin Table 8-1. rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin # Buffer Type Pin Name Pin # Buffer Type PEG_RX#[5] PCIe PEG_TX[4] PCIe PEG_RX#[6] PCIe PEG_TX[5]...
Page 114 Processor Pin and Signal Information Table 8-1. rPGA988B Processor Pin Table 8-1. rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin # Buffer Type Pin Name Pin # Buffer Type RSVD AK32 SA_CKE[1] DDR3 RSVD SA_CS#[0] DDR3 RSVD...
Page 115  Processor Pin and Signal Information Table 8-1. rPGA988B Processor Pin Table 8-1. rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin # Buffer Type Pin Name Pin # Buffer Type SA_DQ[43] DDR3 SA_MA[10] DDR3 SA_DQ[44] DDR3 SA_MA[11]...
Page 116 Processor Pin and Signal Information Table 8-1. rPGA988B Processor Pin Table 8-1. rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin # Buffer Type Pin Name Pin # Buffer Type SB_DQ[24] DDR3 SB_DQS#[7] AP15 DDR3 SB_DQ[25] DDR3 SB_DQS[0]...
Page 117  Processor Pin and Signal Information Table 8-1. rPGA988B Processor Pin Table 8-1. rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin # Buffer Type Pin Name Pin # Buffer Type VAXG AH23 VAXG AT21 VAXG AH24 VAXG...
Page 118 Processor Pin and Signal Information Table 8-1. rPGA988B Processor Pin Table 8-1. rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin # Buffer Type Pin Name Pin # Buffer Type AG28 AG29 AG30 AG31 AG32 AG33 AG34 AG35...
Page 119  Processor Pin and Signal Information Table 8-1. rPGA988B Processor Pin Table 8-1. rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin # Buffer Type Pin Name Pin # Buffer Type VCCIO VCCIO AB26 VCCIO AB27 VCCIO AB28...
Page 120 Processor Pin and Signal Information Table 8-1. rPGA988B Processor Pin Table 8-1. rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin # Buffer Type Pin Name Pin # Buffer Type AN10 AN13 AJ10 AN16 AJ13 AN19 AJ16 AN22...
Page 121  Processor Pin and Signal Information Table 8-1. rPGA988B Processor Pin Table 8-1. rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin # Buffer Type Pin Name Pin # Buffer Type Datasheet, Volume 1...
Page 122 Processor Pin and Signal Information Table 8-1. rPGA988B Processor Pin Table 8-1. rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin # Buffer Type Pin Name Pin # Buffer Type VSS_VAL_SENSE AH33 Analog VSSAXG_SENSE AK34 Analog VSSAXG_VAL_SEN AH31...
Page 123: Bga1224 Ballmap (Top View, Upper-Left Quadrant)
 Processor Pin and Signal Information Figure 8-5. BGA1224 Ballmap (Top View, Upper-Left Quadrant) DC_TES DC_TES VSS_N SB_DQ[ SB_DQ[ SB_DQ[ SM_RC SM_VR SB_BS[ RSVD VDDQ T_BJ64 T_BJ62 OMP[0] DC_TES DC_TES VSS_N SB_DQ[ SB_DQ SB_DQ[ SB_DQ[ SB_DQ SB_DQ[ SB_DQ[ SB_OD SB_CS SB_CAS SB_CK RSVD...
Page 124: Bga1224 Ballmap (Top View, Upper-Right Quadrant)
Processor Pin and Signal Information Figure 8-6. BGA1224 Ballmap (Top View, Upper-Right Quadrant) SB_MA[ SB_CKE SB_DQ[ SB_DQ[ SB_DQ[ VSS_N DC_TES DC_TES RSVD VDDQ RSVD T_BJ4 T_BJ2 SB_CK SB_MA[ SB_MA[ SB_MA[ SB_DQ[ SB_DQ SB_DQ[ SB_DQ[ SB_DQ SB_DQ[ VSS_N DC_TES DC_TES RSVD RSVD RSVD RSVD...
Page 125: Bga1224 Ballmap (Top View, Lower-Left Quadrant)
 Processor Pin and Signal Information Figure 8-7. BGA1224 Ballmap (Top View, Lower-Left Quadrant) VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG...
Page 126: Bga1224 Ballmap (Top View, Lower-Right Quadrant)
Processor Pin and Signal Information Figure 8-8. BGA1224 Ballmap (Top View, Lower-Right Quadrant) FDI0_T FDI0_F eDP_C VCCIO VCCIO VCCIO RSVD RSVD X#[3] SYNC OMPIO FDI0_L FDI1_L eDP_IC VCCIO VCCIO SYNC SYNC OMPO FDI0_T FDI0_T FDI1_T FDI1_F RSVD X[3] X#[2] X[3] SYNC FDI0_T FDI1_T...
Page 127: Bga1224 Processor Ball List By Ball Name
 Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type BCLK Diff Clk DC_TEST_BH3 BCLK# Diff Clk DC_TEST_BH63...
Page 128 Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type FDI0_FSYNC CMOS PEG_RX[3] PCIe FDI0_LSYNC CMOS PEG_RX[4] PCIe...
Page 129  Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type PEG_TX[14] PCIe RSVD BC14 PEG_TX[15] PCIe RSVD...
Page 130 Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type RSVD SA_DQ[18] DDR3 RSVD SA_DQ[19] DDR3 RSVD SA_DQ[20]...
Page 131  Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type SA_DQ[61] AY57 DDR3 SB_CKE[0] BD25 DDR3 SA_DQ[62]...
Page 132 Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type SB_DQ[35] BG50 DDR3 SB_DQS[6] AY65 DDR3 SB_DQ[36] BF49...
Page 133  Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type VAXG AF58 VAXG VAXG AF56 VAXG VAXG...
Page 134 Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type VCC_DIE_SENSE Analog VCC_SENSE Analog VCC_VAL_SENSE Analog VCCDQ AV23...
Page 135  Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type VCCDQ AL23 VCCIO AL15 VCCIO AV55 VCCIO...
Page 136 Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type VCCSA VDDQ AT46 VCCSA VDDQ AT42 VCCSA VDDQ...
Page 137  Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type BJ48 BC40 BJ40 BC36 BJ32 BC32 BJ24...
Page 138 Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type AV63 AP31 AV59 AP25 AV57 AP19 AV50 AP17...
Page 139  Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type AF63 AF61 AF11 AE57 AD16 AD14 AC64...
Page 140 Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball Table 8-2. BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type VSS_NCTF BJ60 VSS_NCTF Datasheet, Volume 1...
Page 141  Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name Ball Name Ball # Buffer Type VSS_NCTF BH61 VSS_NCTF VSS_NCTF BE64 VSS_NCTF VSS_NCTF BD65 VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_SENSE Analog VSS_SENSE_VDDQ AW20 Analog...
Page 142: Bga1023 Ballmap (Top View, Upper-Left Quadrant)
Processor Pin and Signal Information Figure 8-9. BGA1023 Ballmap (Top View, Upper-Left Quadrant) DC_TEST DC_TEST DC_TEST VSS_NCT SB_DQ[4 SB_DQS# SB_ODT[ SM_RCO SA_MA[0 SB_BS[0] VDDQ _BG61 _BG59 _BG58 MP[2] SB_DQ[4 SB_DQ[3 SB_DQ[3 SM_RCO SB_MA[0 SB_RAS# SA_BS[1] MP[0] DC_TEST DC_TEST VSS_NCT SB_DQ[4 SB_DQ[4 SB_DQ[3 SB_DQS[...
Page 143: Bga1023 Ballmap (Top View, Upper-Right Quadrant)
 Processor Pin and Signal Information Figure 8-10. BGA1023 Ballmap (Top View, Upper-Right Quadrant) SB_MA[6 SB_DQ[3 SB_DQ[2 SB_DQS# VSS_NCT DC_TEST DC_TEST DC_TEST RSVD RSVD RSVD _BG4 _BG3 _BG1 SB_CKE[1 SB_DQ[3 SB_DQ[2 SB_DQ[1 SB_DQ[2 RSVD SB_MA[8 SB_MA[9 SB_DQ[2 SB_DQ[2 SB_DQ[2 SB_DQ[2 SB_DQ[2 SB_DQS[ SB_DQ[1...
Page 144: Bga1023 Ballmap (Top View, Lower-Left Quadrant)
Processor Pin and Signal Information Figure 8-11. BGA1023 Ballmap (Top View, Lower-Left Quadrant) VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG...
Page 145: Bga1023 Ballmap (Top View, Lower-Right Quadrant)
 Processor Pin and Signal Information Figure 8-12. BGA1023 Ballmap (Top View, Lower-Right Quadrant) eDP_ICO VCCIO VCCIO VCCIO FDI1_FSY FDI1_TX# FDI1_TX[ eDP_TX#[ eDP_TX#[ eDP_TX[0 VCCIO VCCIO VCCIO FDI0_FSY FDI0_LSY FDI0_TX[ FDI0_TX# eDP_TX[1 FDI1_TX[ VCCIO VCCIO FDI1_TX# FDI0_TX# FDI0_TX[ FDI1_TX[ FDI1_TX# FDI0_TX[ FDI0_TX# VCCSA...
Page 146: Bga1023 Processor Ball List By Ball Name
Processor Pin and Signal Information Table 8-3. BGA1023 Processor Ball Table 8-3. BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type BCLK Diff Clk DC_TEST_BG61 BG61 BCLK# Diff Clk DC_TEST_C4...
Page 147  Processor Pin and Signal Information Table 8-3. BGA1023 Processor Ball Table 8-3. BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type FDI0_TX[2] PEG_RX[15] PCIe FDI0_TX[3] PEG_TX#[0] PCIe FDI1_FSYNC...
Page 148 Processor Pin and Signal Information Table 8-3. BGA1023 Processor Ball Table 8-3. BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type RSVD SA_DQ[2] AP11 DDR3 RSVD BD26 SA_DQ[3] DDR3...
Page 149  Processor Pin and Signal Information Table 8-3. BGA1023 Processor Ball Table 8-3. BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type SA_DQ[49] AV56 DDR3 SA_ODT[0] AY40 DDR3 SA_DQ[50]...
Page 150 Processor Pin and Signal Information Table 8-3. BGA1023 Processor Ball Table 8-3. BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type SB_DQ[31] BF19 DDR3 SB_DQS[6] AR59 DDR3 SB_DQ[32] BD50...
Page 151  Processor Pin and Signal Information Table 8-3. BGA1023 Processor Ball Table 8-3. BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type VAXG AB59 VAXG AB58 VAXG AB56 VAXG...
Page 152 Processor Pin and Signal Information Table 8-3. BGA1023 Processor Ball Table 8-3. BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type VCCIO AL15 VCCIO AL14 VCCIO AK51 VCCIO AK50...
Page 153  Processor Pin and Signal Information Table 8-3. BGA1023 Processor Ball Table 8-3. BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type VCCSA BG41 VCCSA BG37 VCCSA BG28 VCCSA...
Page 154 Processor Pin and Signal Information Table 8-3. BGA1023 Processor Ball Table 8-3. BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type AW13 AM42 AM38 AV55 AM34 AV48 AM30 AV40...
Page 155  Processor Pin and Signal Information Table 8-3. BGA1023 Processor Ball Table 8-3. BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type AF55 AF53 AF52 AF51 AF50 AF48 AF47...
Page 156 Processor Pin and Signal Information Table 8-3. BGA1023 Processor Ball Table 8-3. BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball # Buffer Type Ball Name Ball # Buffer Type VSS_NCTF BG57 VSS_NCTF VSS_NCTF BE58 VSS_NCTF VSS_NCTF BD59...
Page 157: Package Mechanical Information
Processor Pin and Signal Information Package Mechanical Information Figure 8-13. Processor rPGA988B 2C (GT2) Mechanical Package (Sheet 1 of 2) Datasheet, Volume 1...
Page 158: Processor Rpga988B 2C (Gt2) Mechanical Package (Sheet 2 Of 2)
Processor Pin and Signal Information Figure 8-14. Processor rPGA988B 2C (GT2) Mechanical Package (Sheet 2 of 2) Datasheet, Volume 1...
Page 159: Processor Rpga988B 4C (Gt2) Mechanical Package (Sheet 1 Of 2)
Processor Pin and Signal Information Figure 8-15. Processor rPGA988B 4C (GT2) Mechanical Package (Sheet 1 of 2) Datasheet, Volume 1...
Page 160: Processor Rpga988B 4C (Gt2) Mechanical Package (Sheet 2 Of 2)
Processor Pin and Signal Information Figure 8-16. Processor rPGA988B 4C (GT2) Mechanical Package (Sheet 2 of 2) Datasheet, Volume 1...
Page 161: Processor Bga1023 2C (Gt2) Mechanical Package (Sheet 1 Of 2)
Processor Pin and Signal Information Figure 8-17. Processor BGA1023 2C (GT2) Mechanical Package (Sheet 1 of 2) Datasheet, Volume 1...
Page 162: Processor Bga1023 2C (Gt2) Mechanical Package (Sheet 2 Of 2)
Processor Pin and Signal Information Figure 8-18. Processor BGA1023 2C (GT2) Mechanical Package (Sheet 2 of 2) Datasheet, Volume 1...
Page 163: Processor Bga1224 4C (Gt2) Mechanical Package (Sheet 1 Of 2)
Processor Pin and Signal Information Figure 8-19. Processor BGA1224 4C (GT2) Mechanical Package (Sheet 1 of 2) Datasheet, Volume 1...
Page 164: Processor Bga1224 4C (Gt2) Mechanical Package (Sheet 2 Of 2)
Processor Pin and Signal Information Figure 8-20. Processor BGA1224 4C (GT2) Mechanical Package (Sheet 2 of 2) Datasheet, Volume 1...
Page 165: Processor Rpga988B 2C (Gt1) Mechanical Package (Sheet 1 Of 2)
Processor Pin and Signal Information Figure 8-21. Processor rPGA988B 2C (GT1) Mechanical Package (Sheet 1 of 2) Datasheet, Volume 1...
Page 166: Processor Rpga988B 2C (Gt1) Mechanical Package (Sheet 2 Of 2)
Processor Pin and Signal Information Figure 8-22. Processor rPGA988B 2C (GT1) Mechanical Package (Sheet 2 of 2) Datasheet, Volume 1...
Page 167: Processor Bga1023 2C (Gt1) Mechanical Package (Sheet 1 Of 2)
Processor Pin and Signal Information Figure 8-23. Processor BGA1023 2C (GT1) Mechanical Package (Sheet 1 of 2) Datasheet, Volume 1...
Page 168: Processor Bga1023 2C (Gt1) Mechanical Package (Sheet 2 Of 2)
Processor Pin and Signal Information Figure 8-24. Processor BGA1023 2C (GT1) Mechanical Package (Sheet 2 of 2) § § Datasheet, Volume 1...
Page 169: Ddr Data Swizzling
DDR Data Swizzling DDR Data Swizzling To achieve better memory performance and better memory timing; Intel design performed the DDR Data pin swizzling which will allow a better use of the product across different platforms. Swizzling has no effect on functional operation and is invisible to the OS/SW.
Page 170: Ddr Data Swizzling Table - Channel A
DDR Data Swizzling Table 9-1. DDR Data Swizzling Table 9-1. DDR Data Swizzling Table – Channel A Table – Channel A MC Pin MC Pin Pin Name Number Number Number Pin Name Number Number Number Name Name rPGA BGA1023 BGA1224 rPGA BGA1023 BGA1224...
Page 171: Ddr Data Swizzling Table - Channel B
 DDR Data Swizzling Table 9-2. DDR Data Swizzling Table – Channel B Table 9-2. DDR Data Swizzling Table – Channel B Pin Name Number Number Number rPGA BGA1023 BGA1224 Name Pin Name Number Number Number rPGA BGA1023 BGA1224 Name SB_DQ[41] BE57 BH55...
Page 172 DDR Data Swizzling Datasheet, Volume 1...

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