Figure 14-6. 8-Bit Wide Data Bus Bursts - Intel i960 Jx Developer's Manual

8-Bit Burst Bus
Burst accesses for a 16-bit bus are always aligned to even short-word boundaries. A four
short-word burst access always begins on a four short-word boundary (A2=0, A1=0). Two
short-word burst accesses always begin on an even short-word boundary (A1=0). Single
short-word transfers occur on single short-word boundaries (see
Burst accesses for an 8-bit bus are always aligned to even byte boundaries. Four-byte burst
accesses always begin on a 4-byte boundary (A1=0, A0=0). Two-byte burst accesses always begin
on an even byte boundary (A0=0) (see
Figure 14-7 illustrates a series of bus accesses resulting from a triple-word store request to 16-bit
wide memory. The top half of the figure shows the initial location of 12 data bytes contained in
registers g4 through g6. The instruction's task is to move this data to memory at address 0AH. The
top half of the figure also shows the final destination of the data.
Notice that a new 16-byte boundary begins at address 10H. Since the processor stores 6 of the 12
bytes after this 16-byte boundary, the processor will split the transaction into a number of accesses.
The i960 Jx processor cannot burst across 16-byte boundaries.
A1:0 = (BE1, BE0)
00 01 10

Figure 14-6. 8-Bit Wide Data Bus Bursts

Figure 14-6).
EXTERNAL BUS
11
4-Byte Burst
2-Byte Burst
2-Byte Burst
Figure 14-5).
14
14-13