Related Manuals for Intel I3-530
Summary of Contents for Intel I3-530
- Page 1 ® ™ Intel Core i5-600, i3-500 Desktop Processor Series and ® Intel Pentium Desktop Processor 6000 Series Specification Update January 2011 322911-013 Reference Number:...
- Page 2 It may also require modifications of implementation of new business processes. With regard to notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off.
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Page 3: Table Of Contents
Contents Contents Revision History ....................... 5 Preface ..........................6 Summary Tables of Changes ..................8 Identification Information ....................14 Errata ..........................17 Specification Changes....................49 Specification Clarifications ................... 50 Documentation Changes ....................51 § Specification Update... - Page 4 Contents Specification Update...
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Page 5: Revision History
-003 March 2010 Added Documentation Changes AAU1-AAU3. -004 Added Errataum AAU92. April 2010 Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-680 processor. -005 April 2010 Added processor K-0 stepping information. -006 Added Errata AAU93 - AAU97 April 2010 Updated Processor Identification table to include the SKU information for the Intel®... -
Page 6: Preface
This document may also contain information that was not previously published. Affected Documents Document Document Title Number ® ® ® Intel Core™ i5-600, i3-500 Desktop Processor Series and Intel Pentium Desktop 322909-006 Processor 6000 Series Datasheet, Volume 1 ® ® ® Intel Core™... - Page 7 Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products.
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Page 8: Summary Tables Of Changes
Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. - Page 9 Errata (Sheet 1 of 5) Steppings Number Status ERRATA AAU1 No Fix The Processor May Report a #TS Instead of a #GP Fault REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page AAU2 No Fix Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher AAU3...
- Page 10 Errata (Sheet 2 of 5) Steppings Number Status ERRATA Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does AAU26 No Fix Not Work Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May AAU27 No Fix Result in Stuck Core Operating Ratio Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an AAU28 No Fix...
- Page 11 The Memory Controller May Hang Due to Uncorrectable ECC Errors or Parity AAU73 No Fix Errors Occurring on Both Channels in Mirror Channel Mode MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology AAU74 No Fix Core Ratio Multipliers for Non-Existent Core Configurations...
- Page 12 Errata (Sheet 4 of 5) Steppings Number Status ERRATA 2MB Page Split Lock Accesses Combined With Complex Internal Events May AAU77 No Fix Cause Unpredictable System Behavior If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the AAU78 No Fix same time that the APIC timer Current Count Register (Offset 0390H) reads 1H,...
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Page 13: Specification Changes
VM Entry May Omit Consistency Checks Related to Bit 14 (BS) of the Pending AAU107 No Fix Debug Exception Field in Guest-State Area of the VMCS Intel Turbo Boost Technology Ratio Changes May Cause Unpredictable System AAU108 No Fix Behavior... -
Page 14: Identification Information
Identification Information Component Identification using Programming Interface ® ® ® The Intel Core™ i5-600, i3-500 Desktop Processor Series and Intel Pentium Desktop Processor 6000 Series stepping can be identified by the following register contents: Extended Extended Processor Family Model Stepping... - Page 15 INTEL ©'08 PROC# BRAND SLxxx [COO] SPEED/CACHE/FMB [FPO] LOT NO S/N Table 1. Processor Identification (Sheet 1 of 2) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared S-Spec Processor Processor DDR3 (MHz) / Stepping Technology L3 Cache Notes...
- Page 16 Virtualization Technology for IA-32, Intel 64 and Intel Architecture (Intel VT-x) enabled. ® ® Intel Virtualization Technology for Directed I/O (Intel VT-d) enabled. ® Intel AES-NI enabled. Intel SSE4.1 and SSE4.2 enabled. This processor has TDP of 87 W. The core frequency reported in the processor brand string is rounded to 2 decimal digits. (For example, core frequency of 3.4666, repeating 6, is reported as @3.47 in brand string.
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Page 17: Errata
Under certain conditions as described in the Software Developers Manual section "Out- of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this... - Page 18 #GP fault may not match the non-canonical address that caused the fault. Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially- available software. Workaround: None identified.
- Page 19 accessing side-effect memory and by ensuring that all code is written such that a code segment limit violation cannot occur as a part of reading from side-effect memory. Status: For the steppings affected, see the Summary Tables of Changes. AAU6. MOV To/From Debug Registers Causes Debug Exception Problem: When in V86 mode, if a MOV instruction is executed to/from a debug registers, a...
- Page 20 ENTER instructions. This erratum is not expected to occur in Ring 3. Faults are usually processed in Ring 0 and stack switch occurs when transferring to Ring 0. Intel has not observed this erratum on any commercially-available software. Workaround: None identified.
- Page 21 AAU12. General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted Problem: When the processor encounters an instruction that is greater than 15 bytes in length, a #GP is signaled when the instruction is decoded. Under some circumstances, the #GP fault may be preempted by another lower priority fault (e.g., Page Fault (#PF)).
- Page 22 Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section titled "Switching to Protected Mode" recommends the FAR JMP immediately follows the write to CR0 to enable protected mode. Intel has not observed this erratum with any commercially-available software.
- Page 23 If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect. Status: An incorrect error code may be pushed onto the stack. Intel has not observed this erratum with any commercially-available software. Workaround: None identified.
- Page 24 Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially-available software or system.
- Page 25 Thermal Monitor disable. This condition will only correct itself once the processor reaches its TCC activation temperature again. Implication: Since Intel requires that Thermal Monitor be enabled in order to be operating within specification, this erratum should never be seen during normal operation. Workaround: Software should not disable Thermal Monitor during processor operation.
- Page 26 Implication: Memory ordering may be violated. Intel has not observed this erratum with any commercially-available software. Workaround: Software should ensure pages are not being actively used before requesting their memory type be changed.
- Page 27 However, the pending interrupt event will not be cleared. Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the external interrupt. Intel has not observed this erratum with any commercially-available software/system. Workaround: None identified.
- Page 28 EOI register is written and further interrupts from the same or lower priority level will be blocked. Implication: EOI transactions and interrupts may be blocked when core C6 is used during interrupt service routines. Intel has not observed this erratum with any commercially-available software. Workaround: None identified.
- Page 29 AAU39. DR6 May Contain Incorrect Information When the First Instruction After a MOV SS,r/m or POP SS is a Store Problem: Normally, each instruction clears the changes in DR6 (Debug Status Register) caused by the previous instruction. However, the instruction following a MOV SS,r/m (MOV to the stack segment selector) or POP SS (POP stack segment selector) instruction will not clear the changes in DR6 because data breakpoints are not taken immediately after a MOV SS,r/m or POP SS instruction.
- Page 30 10B (All Including Self) or 11B (All Excluding Self). Implication: When this erratum occurs, cores which are in a sleep state may not wake up to handle the broadcast IPI. Intel has not observed this erratum with any commercially-available software. Workaround: Use destination shorthand of 10B or 11B to send broadcast IPIs.
- Page 31 AAU47. Performance Monitor Counters May Count Incorrectly Problem: Under certain circumstances, a general purpose performance counter, IA32_PMC0-4 (C1H - C4H), may count at core frequency or not count at all instead of counting the programmed event. Implication: The Performance Monitor Counter IA32_PMCx may not properly count the programmed event.
- Page 32 None identified. Although the EFLAGS value saved by an affected event (a page fault or an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without fault or VM exit.
- Page 33 Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior Problem: Under a complex set of internal conditions, cores rapidly performing C3/C6 transitions ® in a system with Intel Hyper-Threading Technology enabled may cause a machine check error (IA32_MCi_STATUS.MCACOD = 0x0106), system hang or unpredictable system behavior. Implication: This erratum may cause a machine check error, system hang or unpredictable system behavior.
- Page 34 Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected Problem: x87 instructions that trigger #MF normally service interrupts before the #MF. Due to this erratum, if an instruction that triggers #MF is executed while Enhanced Intel ® ® SpeedStep...
- Page 35 AAU59. VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction Problem: If VM entry is executed with the "NMI-window exiting" VM-execution control set to 1, a VM exit with exit reason "NMI window" should occur before execution of any instruction if there is no virtual-NMI blocking, no blocking of events by MOV SS, and no blocking of events by STI.
- Page 36 The "From" address associated with the LBR (Last Branch Record), BTM (Branch Trace Message) or BTS (Branch Trace Store) may be incorrect for the first branch after an ® EIST (Enhanced Intel SpeedStep Technology) transition, T-states, C1E (C1 Enhanced), or Adaptive Thermal Throttling.
- Page 37 Hyper-Threading Technology is disabled, the Performance Monitor events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may indicate a higher occurrence of loads blocked by stores than have actually occurred. If Intel Hyper-Threading Technology is enabled, the counts of loads blocked by stores may be unpredictable and they could be higher or lower than the correct count.
- Page 38 The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially-available software.
- Page 39 Intel Turbo Boost Technology value will be returned for non-existent core configurations. Implication: Due to this erratum, software using the MSR_TURBO_RATIO_LIMIT MSR to report Intel Turbo Boost Technology processor capabilities may report erroneous results. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
- Page 40 Implication: This erratum may cause unpredictable system behavior. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
- Page 41 Implication: The second PCIe port and therefore any device connected to the PCIe bus instantiated by that PCIe port may not be functional after a warm reset. Intel has not observed this erratum with any commercially available system. Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum.
- Page 42 Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor reset. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.
- Page 43 Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit FP load around a 4-Gbyte boundary in this way is not a normal programming practice. Intel has not observed this erratum with any commercially available software. Workaround:...
- Page 44 SS.B bit is 1 and the adjustment will be to the 32-bit ESP register. Due to this erratum, the adjustment will incorrectly be made to the 16-bit SP register. Intel has not observed this erratum with any commercially available software.
- Page 45 Due to this erratum, the count value for some uncore Performance Monitoring Events may be inaccurate. The degree of under or over counting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observedthis erratum with any commercially available software.
- Page 46 Implication: All fixed-function performance counters will be disabled after an affected VM exit, even if the VM exit should have enabled them based on the IA32_PERF_GLOBAL_CTRL field in the guest-state area of the VMCS. Workaround: A VM monitor that wants the fixed-function performance counters to be enabled after a VM exit may do one of two things: (1) clear the “load IA32_PERF_GLOBAL_CTRL”...
- Page 47 Problem: When the integrated graphics engine continuously generates a large stream of writes to system memory, and Intel Flex Memory Technology is enabled, with a different amount of memory in each channel, the memory arbiter may temporarily stop servicing other device-initiated traffic.
- Page 48 Status: For the steppings affected, see the Summary Tables of Changes. AAU108. Intel Turbo Boost Technology Ratio Changes May Cause Unpredictable System Behavior Problem: When Intel Turbo Boost Technology enabled determined TURBO_MODE_DISABLE bit being “0” in the IA32_MISC_ENABLES MSR (1A0H), the process of locking to new ratio may cause the processor to run with incorrect ratio settings.
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Page 49: Specification Changes
The Specification Changes listed in this section apply to the following documents: ® ® ® • Intel Core™ i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 Datasheet - Volumes 1 and 2 ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ®... -
Page 50: Specification Clarifications
The Specification Clarifications listed in this section may apply to the following documents: ® ® ® • Intel Core™ i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 Datasheet - Volumes 1 and 2 ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ®... -
Page 51: Documentation Changes
The Documentation Changes listed in this section apply to the following documents: ® ® ® • Intel Core™ i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 Datasheet - Volumes 1 and 2 ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ®...