Table of Contents
Advertisement
This chapter describes the i960
local registers, control registers, literals, processor-state registers and address space.
3.1
OVERVIEW
The i960 architecture defines a programming environment for program execution, data storage and data
manipulation.
Figure 3-1
shows the programming environment elements that include the following:
32
•
4 Gbyte (2
byte) flat address space
•
instruction cache
•
data cache
•
global and local general-purpose registers
The processor includes several architecturally-defined data structures located in memory as part of
the programming environment. These data structures handle procedure calls, interrupts and faults
and provide configuration information at initialization. These data structures are:
•
interrupt stack
•
local stack
•
supervisor stack
3.2
REGISTERS AND LITERALS AS INSTRUCTION OPERANDS
With the exception of a few special instructions, the i960 Jx processor uses load and store instruc-
tions to access memory. All operations take place at the register level. The processor uses 16 global
registers, 16 local registers and 32 literals (constants 0-31) as instruction operands.
The global register numbers are g0 through g15; local register numbers are r0 through r15. Several
of these registers are used for dedicated functions. For example, register r0 is the previous frame
pointer, often referred to as pfp. The i960 processor compilers and assemblers recognize only the
instruction operands listed in
numbers, operands and acronyms are used interchangeably, as dictated by context.
PROGRAMMING ENVIRONMENT
®
Jx processor's programming environment including global and
•
•
•
•
•
control table
•
fault table
•
interrupt table
Table
3-1. Throughout this manual, the registers' descriptive names,
CHAPTER 3
register cache
set of literals
control registers
set of processor state registers
•
system procedure table
•
process control block
•
initialization boot record
3
3-1
Advertisement
Table of Contents
