Peripheral Local Bus; Peripheral Bus Signals; Address/Data Signal Definitions; Control/Status Signal Definitions - Intel 80331 Design Manual

Peripheral Local Bus

The Peripheral Bus Interface Unit (PBI) is a data communication path to Flash memory components and
peripherals of a 80331 hardware system. The PBI allows the processor to read and write data to these
supported flash components and other peripherals. To perform these tasks at high bandwidth, the bus
features a burst transfer capability which allows successive 8- or 16-bit data transfers.
The peripheral bus is controlled by the on-chip bus masters: the Intel XScale
AAU and DMA units.
The address/data path is multiplexed for economy, and the bus width is programmable to 8-, and
16-bit widths. The PBI performs the necessary packing and unpacking of bytes to communicate
properly across the 80331 Internal Bus.
The PBI unit includes two chip enables.The PBI chip enables activate the appropriate peripheral
device when the address falls within one of the PBI's two programmable address ranges. Both
address ranges incorporate functionality that optimizes an interface for Flash Memory devices.
8.1

Peripheral Bus Signals

Bus signals consist of two groups: address/data, and control/status.
8.1.1

Address/Data Signal Definitions

The address/data signal group consists of 26 lines. 16 of these signals multiplex within the processor to
serve a dual purpose. During and address cycle (T
the address of the bus access. At all other times, the AD[15:0] lines are defined to contain data. A[2:0]
are demultiplexed address pins providing incrementing byte addresses during burst cycles.
8.1.2

Control/Status Signal Definitions

The control/status signals control peripheral device enables and direction. All output control/status
signals are three-state.
The PBI pulses ALE (address latch enable) active high for one clock during T
multiplexed address on AD[15:2] in external address latches.
A peripheral read may be either non-burst or burst. A non-burst read ends after one data transfer to
a single location.
When the data bus is configured for 16 bits, demultiplexed address bits A[2:1] are used to burst
across up to four short-words. For an 8-bit data bus, demultiplexed address bits A[1:0] are used to
burst across up to four bytes.
Note: Burst write accesses to Flash Devices are not supported.
Intel® 80331 I/O Processor Design Guide
, the processor drives A[22:16] and AD[15:0] with
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Peripheral Local Bus
8
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core, the ATU,
to latch the
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