Table of Contents
Advertisement
Table 12-3. Fail Codes For BIST (bit 7 = 1)
Bit
6
5
4
3
2
1
0
Table 12-4. Remaining Fail Codes (bit 7 = 0)
Bit
6
5
4
3
2
1
0
12.3
Architecturally Reserved Memory Space
The i960 Jx microprocessor contains 2
architecturally reserved and must not be used.
(pg. 3-13)
shows the reserved address space. The i960 Jx suppresses all external bus cycles from 0
to 3FFH and from FF00 0000H to FFFF FFFFH.
Addresses FEFF FF60H through FFFF FFFFH are reserved for implementation-specific functions.
This address range is termed "reserved" since i960 architecture implementations may use these
addresses for functions such as memory-mapped registers or data structures. Therefore, to ensure
complete object level compatibility, portable code must not access or depend on values in this region.
INITIALIZATION AND SYSTEM REQUIREMENTS
When set:
On-chip Data-RAM failure detected by BIST
Internal Microcode ROM failure detected by BIST
I-cache failure detected by BIST
D-cache failure detected by BIST
Local-register cache or processor core (RF, EU,
MDU, PSQ) failure detected by BIST
Always Zero.
Always Zero.
When set:
Always One; this bit does not indicate a failure.
Always One; this bit does not indicate a failure.
A data structure within the IMI is not aligned to a
word boundary.
A System Error during normal operation has
occurred.
The Bus Confidence test has failed.
Always Zero.
Always Zero.
32
bytes of address space. Portions of this address space are
Section 3.5, "MEMORY ADDRESS SPACE"
12
12-9
Advertisement
Table of Contents
