Core i7, i5, and i3 desktop processor series, pentium processor g800 and g600 series, celeron processor g500 and g400 series (112 pages)
Summary of Contents for Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor
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® ® Intel Itanium Processor 9300 Series and 9500 Series ® ® Intel Itanium Processor Quad-Core 1.86-1.73 GHz with 24 MB L3 Cache 9350 ® ® Intel Itanium Processor Quad-Core 1.73-1.60 GHz with 20 MB L3 Cache 9340 ® ®...
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PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A “Mission Critical Application” is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU...
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2-13 VCCUNCORE Static and Transient Tolerance for the ® ® Intel Itanium Processor 9500 Series ..............50 ® ® 2-14 VCCUNCORE Load Line for the Intel Itanium Processor 9500 Series ..... 50 ® ® 2-15 VCCCORE Load Line for the Intel Itanium Processor 9500 Series ......51 2-16 VR Sense Point (Representation) .................
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Processor 9300 Series Clock Frequency Table.........29 ® ® ® Intel Itanium Processor 9300 Series Transmitter Parameter Values for Intel QuickPath Interconnect and Intel SMI Channels @ 4.8 GT/s ........29 ® ® Intel Itanium Processor 9300 Series Receiver Parameter ® ®...
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2-34 Debug Signal Group DC Specifications..............56 2-35 PIROM Signal Group DC Specifications ..............56 2-36 Intel® Itanium® Processor 9300 Series VCCCORE (VID_VCCCORE) and VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for Ararat ..58 2-37 Intel® Itanium® Processor 9500 Series VCCCORE (VID_VCCCORE) and VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for Ararat II ..................
Revision History Document Revision Description Date Number Number 322821 -002 • Initial release of the 9300/9500 document. November 2012 322821 -001 • Initial release of the document. February 2010 § ® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet...
Itanium Processor 9500 Series ® system interface, with its 4 full width and 2 half width Intel QuickPath Interconnects, enables each processor to directly connect to other system components, thus can be used as an effective building block for very large systems. The balanced core and memory subsystem provide high performance for a wide range of applications ranging from commercial workloads to high performance technical computing.
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Introduction ® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet...
QuickPath Interconnect for of processor resources. multiprocessor scalability: — Support for predication and speculation. — 4 full and 2 half width Intel QPI Links — 4.8GT/s transfer rate. Extensive RAS features for business-critical applications, for example: — Systems are easily scaled without sacrificing performance.
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Three levels of on-die cache minimize overall memory latency. It interfaces with the Ararat ® ® “1” Voltage Regulator Module, which used exclusively with the Intel Itanium Processor 9300 Series. ®...
— Built-in processor information ROM (PIROM). multiprocessor scalability: — Built-in programmable EEPROM. — 4 full and 2 half width Intel QPI Links — Hot Plug Socket. — 6.4GT/s transfer rate with aggregate data — Hot-add and hot removal support.
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® The Intel Itanium Processor 9500 Series offers a new RAS feature: Intel Instruction Replay Technology. Pipeline replay resolves stall conditions that occur when the microprocessor pipeline encounters a resource hazard that prevents immediate execution. In a replay, the instruction that encountered the resource hazard is removed from the pipeline, along with all the instructions that come after it.
Itanium Processor 9300 Series block diagram. The Intel QPI viral and poison fields are used to flag corrupted system state and bad data accordingly. Once it has “gone viral”, an Intel QPI agent will set the viral field within all packet headers. Viral mode is entered in three ways: receiving a viral packet, upon a detecting fatal/panic error, or when a global viral signal (from Cboxes) is asserted.
Last Level Cache via the Cache Controllers (Cboxes). The Ring also provides connectivity to Intel QPI via Ring/Sbox. The Sbox and Cbox provide the supports for the two Intel QPI Caching Agents. The processor has two Home Agents ®...
Itanium Processor 9500 Series Processor Block Diagram The Intel QPI viral and poison fields are used to flag corrupted system state and bad data accordingly. Once it has “gone viral”, an Intel QPI agent will set the viral field within all packet headers. Viral mode is entered in three ways: receiving a viral packet, upon a detecting fatal/panic error, or when a global viral signal (from Cboxes) is asserted.
Please see the processor-specific documentation for further information on the number of protection key registers and protection key bits implemented on the processor. ® ® Figure 1-3. Intel Itanium Processor 9500 Series Firmware Diagram ® ® Intel...
Intel Itanium Processor 9300 Series with Intel Itanium Processor 9500 Series is not supported and has not been validated by Intel. Operating system support for multiprocessing with mixed components should also be considered. Terminology ® ®...
State of Data The data contained in this document is subject to change. It is the best information that Intel is able to provide at the publication date of this document. Reference Documents The reader of this specification should also be familiar with material and concepts...
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Introduction ® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet...
(D+, D-) signals, is V Termination resistors are provided on the processor silicon and are terminated to V thus eliminating the need to terminate the links on the system board for the Intel ® QuickPath Interconnect and FB-DIMM signals.
Signal Groups (Sheet 1 of 3) Signal Group Buffer Type Signals 1, 2, 3 Differential System Reference Clock Differential CMOS In Differential Pair SYSCLK, SYSCLK_N; SYSUTST_REFCLK_N, SYSUTST_REFCLK ® Intel QuickPath Interconnect Signal Groups Differential Input CSI[3:0]R[P/N]Dat[19:0], CSI[5:4]R[P/N][9:0] CSI[5:0]R[P/N]CLK Differential Output CSI[3:0]T[P/N]Dat[19:0], CSI[5:4]T[P/N][9:0], CSI[5:0]T[P/N]CLK...
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SVD_DATIO GTL Input SVID_ALERT_N Voltage Regulator Single-ended Open Collector/Drain Output VR_THERMTRIP_N, VRPWRGD (Intel ® Itanium ® Processor 9300 Series processor), VR_READY (Intel ® ® Itanium Processor 9500 Series processor), VR_FAN_N Voltage Regulator Control Single-ended CMOS Input VROUTPUT_ENABLE0 GTL Input VR_THERMALERT_N...
V specification for that buffer. Reference Clocking Specifications ® The processor has one input reference clock, SYSCLK/SYSCLK_N for the Intel interface. The processor timing specified in this section is defined at the processor pins unless otherwise noted. ®...
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Electrical Specifications Table 2-3. Intel ® QuickPath Interconnect/Intel ® Scalable Memory Interconnect Reference Clock Specifications (Sheet 2 of 2) Symbol Parameter Units Notes Allowed time before ringback 3, 10 Stable Accumulated rms jitter over n UI of a given PLL model output in response to the jittery reference clock input.
Intel Itanium Processor 9300 Series Intel QuickPath ® Interconnect and Intel SMI Specifications for 4.8 GT/s The applicability of this section applies to Intel ® QPI for the Intel ® Itanium ® Processor 9300 Series. This section contains information for Intel ®...
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® Table 2-5. Intel Itanium Processor 9300 Series Transmitter Parameter Values for ® Intel QuickPath Interconnect and Intel SMI Channels @ 4.8 GT/s (Sheet 1 of Symbol Parameter Units Notes Average UI size at 4.8 GT/s 208.33 # of UI over which the eye mask voltage and...
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Table 2-5. Intel ® Itanium ® Processor 9300 Series Transmitter Parameter Values for ® Intel QuickPath Interconnect and Intel SMI Channels @ 4.8 GT/s (Sheet 2 of Symbol Parameter Units Notes Transmitter clock or data duty cycle at the -0.076 0.076...
Electrical Specifications Table 2-6. Intel ® Itanium ® Processor 9300 Series Receiver Parameter Values for Intel ® ® QuickPath Interconnect and Intel SMI Channels @ 4.8 GT (Sheet 2 of 2) Symbol Parameter Units Notes Minimum eye width at pin for clk and data...
Itanium Processor 9500 Series Requirements for ® Intel QuickPath Interconnect for 4.8 and 6.4 GT/s The applicability of this section applies to Intel ® Itanium ® Processor 9500 Series. This section contains information for slow boot up speed (1/4 frequency of the reference clock), 4.8 GT/s, and 6.4 GT/s, for Intel...
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66.66 MT/s (see note 1) 2.40 GHz 4.8 GT/s 3.2 GHz 6.4 GT/s Notes: 1. This speed is the 1/4 SysClk Frequency. The applicability of this section applies to Intel ® QPI for the Intel ® Itanium ® Processor 9500 Series. This section contains information for slow boot up speed (1/4 frequency of the reference clock), 4.8 GT/s, and 6.4 GT/s.
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1. Used during initialization. It is the state of “OFF” condition for the receiver when only the minimum termination is connected. ® ® Table 2-9. Intel Itanium Processor 9500 Series Transmitter and Receiver Parameter ® Values for Intel QPI Channel at 4.8 GT/s (Sheet 1 of 2) Symbol Parameter Unit Notes Transmitter differential swing 1400 Tx-diff-pp-pin DC resistance of Tx terminations 37.4...
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Electrical Specifications Table 2-9. Intel ® Itanium ® Processor 9500 Series Transmitter and Receiver Parameter ® Values for Intel QPI Channel at 4.8 GT/s (Sheet 2 of 2) Symbol Parameter Unit Notes p-p accumulated jitter out of 0.15 clk-acc-jit-N_UI-1E-7 transmitter over 0 <= n <= N UI where N=12, measured with 1E-7 probability.
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Electrical Specifications Table 2-10. Intel ® Itanium ® Processor 9500 Series Transmitter and Receiver Parameter ® Values for Intel QPI at 6.4 GT/s (Sheet 2 of 2) Symbol Parameter Unit Notes Transmitter output AC common -0.0375 0.0375 Fraction of Tx-cm-ac-pin...
Processor 9500 Series Processor ® Requirements for Intel SMI Specifications for 6.4 GT/s ® This section defines the high-speed differential point-to-point signaling link for Intel ® ® SMI for the Intel Itanium Processor 9500 Series. The link consists of a transmitter and a receiver and the interconnect between them.
Processor Absolute Maximum Ratings ® ® Table 2-13 specifies absolute maximum and minimum ratings for the Intel Itanium Processor 9300 Series. Within operational maximum and minimum limits, the processor functionality and long-term reliability can be expected. The processor maximum ratings listed in...
® ® Table 2-15 through Table 2-35 list the DC specifications for the Intel Itanium Processor 9300 Series and 9500 Series and are valid only while meeting specifications for case temperature, clock frequency, and input voltages. The following notes apply: ®...
170 W SKUs for the Intel Itanium Processor 9500 Series. Current specifications are identified for each processor SKU separately in Table 2-19. ® ® Table 2-15. FMB Voltage Specifications for the Intel Itanium Processor 9300 Series Symbol Parameter Units Notes VCCCORE VID Range 1.35...
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Step 1 = set both: scope diff probe and/or the scope at 1 MHz BW limit (capture waveform B, channel 2). Step 2 = calculate A-B (use scope Math function: subtract channel 1 - channel 2). ® ® Table 2-16. FMB 130W Current Specifications for the Intel Itanium Processor 9300 Series...
Electrical Specifications ® ® Table 2-17. FMB 155W/185W Current Specifications for the Intel Itanium Processor 9300 Series Symbol Parameter Units Notes for core CC_CORE Thermal Design Current for Core CC_CORE_TDC Max Load step for core CC_CORE_STEP Slew rate for core at Ararat output...
170 W SKUs for the Intel Itanium Processor 9500 Series. Current specifications are identified for each processor SKU separately in Table 2-19. ® ® Table 2-18. FMB Voltage Specifications for the Intel Itanium Processor 9500 Series Symbol Parameter Units Notes CVID VCCCORE VID Range 0.800...
5. During system power on, the pulse inrush (ICC_UNCORE_STEP) can be as high as 40A peak-to-peak. 6. The ICC_IO current specification applies to the total current from VCCIO pins. ® ® 7. The max load step represents the maximum current required during Intel QPI and Intel SMI port initialization. The min time ®...
Electrical Specifications ® ® Table 2-20. V Static and Transient Tolerance for Intel Itanium Processor 9300 UNCORE Series Uncore Voltage Deviation from VID Setting (V)1,2,3,4 Current (A) CC_UNCORE CC_Max CC_Typ CC_Min VID - 0 VID - 0.02 VID - 0.04 VID - 0.02...
Electrical Specifications 2.6.3.2 Core Static and Transient Tolerances Table 2-21 Figure 2-11 specify static and transient tolerances for the core outputs. Table 2-21. V Static and Transient Tolerance for Intel ® Itanium ® Processor 9300 CORE Series (Sheet 1 of 2)
Electrical Specifications Table 2-21. V Static and Transient Tolerance for Intel ® Itanium ® Processor 9300 CORE Series (Sheet 2 of 2) Core Current (A) Voltage Deviation from VID Setting (V)1,2,3,4 CC_CORE CC_Max CC_Typ CC_Min VID - 0.145 VID - 0.165 VID - 0.185...
Electrical Specifications ® ® Table 2-22. V Static and Transient Tolerance for Intel Itanium Processor 9300 CACHE Series Cache Current (A) Voltage Deviation from VID Setting (V)1,2,3,4 CC_CACHE CC_Max CC_Typ CC_Min VID - 0 VID - 0.02 VID - 0.04 VID - 0.017...
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Uncore Static and Transient Tolerances Table 2-23 Figure 2-13 specify static and transient tolerances for the uncore outputs. ® ® Table 2-23. V Static and Transient Tolerance for the Intel Itanium Processor UNCORE 9500 Series Uncore Voltage Deviation from VID Setting (V)1,2,3,4 Current (A)
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Electrical Specifications ® ® Figure 2-13. V Static and Transient Tolerance for the Intel Itanium Processor UNCORE 9500 Series VccUnCore Tolerance Band 0.0150 VccUnCore ACMax (V) -0.0050 VccUnCore DCMax (V) Normalized VccUnCore (V) -0.0250 VccUnCore DCMin (V) -0.0450 VccUnCore ACMin (V) -0.0650...
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Electrical Specifications ® ® Table 2-24. V Static and Transient Tolerance for the Intel Itanium Processor CORE 9500 Series Core Current (A) Voltage Deviation from VID Setting (V)1,2,3,4 CC_CORE CC_Max CC_Typ CC_Min VID + 0.015 VID - 0.015 VID + 0.005 VID - 0.010...
The overshoot and undershoot specifications listed in the following table specify the allowable overshoot or undershoot for a single overshoot or undershoot event. ® ® Table 2-25 specifies the maximum overshoot and undershoot for the Intel Itanium Processor 9300 Series, while Table 2-26 specifies the maximum overshoot and under- shoot for the Intel ®...
-0.525 ABSMAX-US-DIFF signals Sysclk single-ended maximum voltage 1.54 MAX_OS_SYSCLK Sysclk single-ended minimum voltage -0.337 MIN_US_SYSCLK 2.6.5.2.2 Overshoot and Undershoot Specifications for the Intel ® Itanium ® Processor 9500 Series Table 2-26. Overshoot and Undershoot Specifications For Differential ® ® Intel...
Voltage Regulator Module Design Guide or the Ararat II Voltage Regulator Module Design Guide for I max. 3. See Intel ® Itanium ® 9300 Series and Intel ® Itanium ® 9500 Series Platform Design Guide for recommended resistor values. 4. VR_THERMALERT_N is an input to the top of the package and an output from the bottom of the package. V and V levels are for the input at the top of the package, sensed by the processor;...
Voltage levels are compliant to the VR12.0 1V TTL signaling requirements and are shown in Table 2-32. Table 2-32. SVID Group DC Specifications for the Intel ® Itanium ® Processor 9500 Series...
(min) and V (max) are reference only and are not tested. 2. Applicable over recommended operating range T = -40 °C to +88 °C; Vcc = +1.7 V to +3.6 V. ® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet...
The VID_VCCCORE[6:0] and VID_VCCUNCORE[6:0] lands supply the encoding that determine the voltage to be supplied by the VCCCORE and VCCUNCORE voltage ® regulators. The VID_VCCCORE and VID_VCCUNCORE specifications for the Intel ® Itanium Processor 9300 Series and 9500 Series are defined in the Ararat 170 Watt Voltage Regulator Module Design Guide and Ararat II Voltage Regulator Module Design Guide, respectively.
Electrical Specifications 2.7.1 Core and Uncore Voltage Identification for the Intel® Itanium® Processor 9300 Series Table 2-36. Intel® Itanium® Processor 9300 Series VCCCORE (VID_VCCCORE) and VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for Ararat (Sheet 1 of 2) VID6 VID3 VID (V)
All RSVD (RESERVED) pins must be left unconnected. Connection of these pins to power, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. ® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet...
2.10 Mixing Processors Intel will support mixing CPUs in the same system or hard partition as defined below. A hard partition is a smaller system capable of booting an OS, consisting of one or more processors, memory and I/O controller hubs that are formed by domain partitioning.
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Itanium Processor 9500 Series. When the platform asserts PWRGOOD to the processor, the Intel® Itanium® Processor 9300 Series requires a minimum of 10 ms to complete its internal reset sequence before deasserting RESET_N, while the Intel® Itanium® Processor 9500 Series requires a minimum of 15 ms.
Figure 2-17. Supported Power-up Voltage Sequence Timing Requirements for the Intel® Itanium® Processor 9300 Series VCC33_SM (3.3v) >1uS >0uS PROCTYPE pulled to VSS on package for Intel® Itanium® processor 9300 series (VCC33_SM for other products) >0us VccArarat (12V) >= 0us VCCA (1.8V) >=0us VCCIO >1us *...
Delay from VCCCORE/VCCUNCORE/VCCCACHE at programmed 0.05 values to VRPWRGOOD high for Intel ® Itanium ® Processor 9300 Series VRPWRGD high to PWRGOOD high for Intel® Intel ® Itanium ® >0 Processor 9300 Series VR_READY high to PWRGOOD high for Intel ®...
The LRGSCLSYS pin is sampled only during the PWRGOOD and cold reset period. The BOOTMODE[2:0] and FLASHROM_CFG[1:0] pins are sampled during the assertion of all resets except warm-logic resets. ® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet...
BOOTMODE[2:0], FLASHROM_CFG[1:0] hold after RESET_N deasserted BOOTMODE[2:)], FLASHROM_CFG[1:0] setup to RESET_N asserted 2.14 Test Access Port (TAP) Connection ® ® The recommended TAP connectivity is detailed in the Intel Itanium Platform Debug Port Design Guide (DPDG). § ® ® Intel...
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Electrical Specifications ® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet...
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29 of 32) 30 of 32) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type ® CSI0RNDAT[13] Differential RSVD (Intel ® Itanium Processor CSI0RPDAT[13] Differential 9300 Series) ® SVID_ALERT_N (Intel Power/Other ® Itanium Processor Power/Other 9500 Series)
This section provides two-dimensional tables of the package top pin assignments. These pins connect to the Ararat Voltage Regulator Power Module and do not connect to the motherboard. 3.2.1 Top-Side J1 Connector Two-Dimensional Table 3.2.1.1 Top-Side J1 Connector Two-Dimensional Table for the Intel ® Itanium ® Processor 9300 Series ®...
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NO CONNECT NO CONNECT VROUTPUT_ENABLE0 CPU_PRESA_N VR_PROCTYPE_0 VR_PROCTYPE_1 ® ® 3.2.1.2 Top-Side J1 Connector Two-Dimensional Table for the Intel Itanium Processor 9500 Series ® ® Table 3-4 is a two-dimensional table of the Intel Itanium Processor 9500 Series package top-side J1 connector.
NO CONNECT NO CONNECT VR_THERMALERT_N VSSCORESENSE VID_VCCCORE[0] CPU_PRESB_N ® ® 3.2.2.2 Top-Side J2 Connector Two-Dimensional Table for the Intel Itanium Processor 9500 Series ® ® Table 3-6 is a two-dimensional table of the Intel Itanium Processor 9500 Series package top-side J2 connector.
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Pin Listing ® ® Table 3-6. Top-Side J2 Connector Two-Dimensional Table (Intel Itanium Processor 9500 Series) (Sheet 1 of 2) NO CONNECT NO CONNECT NO CONNECT VR_READY NO CONNECT NO CONNECT RESERVED RESERVED VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE...
NO CONNECT NO CONNECT NO CONNECT 3.2.3 Top-Side J3 Connector Two-Dimensional Table ® ® 3.2.3.1 Top-Side J3 Connector Two-Dimensional Table for the Intel Itanium Processor 9300 Series ® ® Table 3-7 is a two-dimensional table of the Intel Itanium Processor 9300 Series package top-side J3 connector.
Pin Listing ® ® 3.2.3.2 Top-Side J3 Connector Two-Dimensional Table for the Intel Itanium Processor 9500 Series ® ® Table 3-8 is a two-dimensional table of the Intel Itanium Processor 9500 Series package top-side J3 connector. ® ® Table 3-8.
CPU_PRESB_N NO CONNECT Reserved 3.2.4 Top-Side J4 Connector Two-Dimensional Table ® ® 3.2.4.1 Top-Side J4 Connector Two-Dimensional Table for the Intel Itanium Processor 9300 Series Table 3-9 is a two-dimensional table of the Intel ® Itanium ® Processor 9300 Series package top-side J4 connector.
Mechanical Specifications Mechanical Specifications ® ® The Intel Itanium Processor 9300 Series and 9500 Series are packaged in a FC-LGA package that interfaces with the motherboard via an LGA1248 socket. The package top side consists of lands that interface with a LGA connector for direct power delivery to the core, cache and system interface.
Package Mechanical Drawing The package mechanical drawings are shown in Figure 4-2, Figure 4-3, Figure 4-4 Figure 4-5. The package mechanical drawings for the Intel® Itanium® Processor 9500 Series processor are shown in Figure 4-6, Figure 4-7, Figure 4-8 Figure 4-9.
A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to both ® the top-side and bottom-side of the package substrate. See Figure 4-4 for Intel ® ® ® Itanium...
VID (Visual Identification): Is a unique number which can be used for the purpose of tracking the processor. It is used by Intel to retrieve processor related information. FPO (Finish Process Order): Is a unique number. It can be used for tracking purposes. It is used by Intel to retrieve processor and shipping order information.
Mechanical Specifications Figure 4-10. Processor Marking Zones Top Side Bottom Side § ® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet...
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Mechanical Specifications ® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet...
It provides several hooks to the OS and system management to monitor and change the processor performance and thermal status. ® ® With the power and thermal management system on the Intel Itanium Processor 9300 Series and Intel ®...
QR_CSR_IPF_THERM_STATUS.valid = 1’b0. ® ® 5.1.1.1 Thermal Sensor Accuracy Distribution for the Intel Itanium Processor 9300 Series Table 5-1 shows the processor thermal sensor accuracy with respect to the DT readout ®...
Table 5-2 shows the processor thermal sensor accuracy with respect to the DT readout for the Intel® Itanium® Processor 9500 Series . The margin of error is relative to PROCHOT and represents the typical ±3-sigma range. For the Intel® Itanium®...
Another PAL call will return the processor to normal operation. These special modes are intended for debug purposes only. 5.1.3 Thermal Alert ® THERMALERT_N is a programmable thermal alert signal which is part of the Intel Intel ® ® ® Itanium...
If THERMTRIP_N is asserted, processor voltages (VCCCORE, VCCUNCORE, AND VCCCACHE) must be removed within the timeframe defined in Table 2-36. ® ® Data will be lost or corrupt, and transaction time outs will occur if the Intel Itanium ® ® Processor 9300 Series and Intel Itanium Processor 9500 Series go into thermal trip.
® ® The Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series package allows the Ararat Voltage Regulator to signal to the platform when it approaches its own thermal limits. The specific signals for this purpose are VR_FAN_N, VR_THERMALERT_N, and VR_THERMTRIP_N.
The processor maximum temperature is reached at T . That is when DT readout is equal to zero. PROCHOT Intel recommends that the thermal solution designs target the processor Thermal Design Power (TDP), instead of its spontaneous maximum power consumption. Processor TDP is determined at the T...
Non operating storage condition limits for the component once installed onto the application board are not specified. Intel does not conduct component level certification assessments post subsequent applications such as components sub-assembly (FRU: Field Replaceable Unit), or installation onto a board given the multitude of attach methods, and board types used by customers.
For functional operation, please refer to the processor case temperature specifications. These ratings apply to the Intel component and do not include the tray or packaging. Failure to adhere to this specification can affect the long-term reliability of the processor.
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Thermal Specifications ® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet...
6.4. The processor SMBus implementation uses the clock and data signals of the System Management Bus (SMBus) Specification. Layout and routing guidelines are available in the Intel® Itanium® 9300 Series and Intel® Itanium® 9500 Series Platform Design Guide. ® ®...
Processor Sample/Production Identifies sample parts separately 0x01 = Production from production parts 0x00 = Sample Voltage Regulator Type Identifies Ararat type required 0x00 for Intel® Required Itanium® Processor 9300 Series, 0x01 for Intel® Itanium® Processor 9500 Series VCCA 4 binary coded Processor Analog Voltage Supply 1.800V = 1800...
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1733 MHz = 1733 frequency of this part in MHz (Intel® Itanium® (Intel® Itanium® 26h = 33 Processor 9300 Series) Processor 9300 (Intel® Itanium® Processor 9300 27h = 17 Series) Series) (Intel® Itanium® Processor 9300 Series) 2 bcd digits (0x26)
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47h = 00 Cache Voltage ID 4 bcd digits Voltage in four 4-bit bcd digits (in 1163 mV = 1163 (Intel® Itanium® mV) (Intel® Itanium® Processor (Intel® Itanium® 48h = 63 Processor 9300 9300 Series) Processor 9300 Series) 49 = 11 Series) (Intel®...
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(Intel® Itanium® 6 Bits reserved (LSB) 9300 Series) Processor 9300 Series) (Intel® Itanium® Processor 9300 Series) 0x00 (Intel® Itanium® Reserved for future use for Intel® RESERVED (Intel® Processor 9500 Series) Itanium® Processor 9500 Series Itanium® Processor 9500 Series) Checksum Add up by byte and take 2's...
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Base Core Frequency for this part f = 1600 Mhz 65h = 00 66h = 16 RESERVED (Intel® 4 bcd digits Reserved for future use (Intel® 67h = 0x00 Itanium® Processor Itanium® processor 9300 series) 68h = 0x00 (Intel® 9300 Series) Itanium®...
® ® The Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series PIR_A[1:0] pins are used as the memory address selection signals. The processor does not specify the value on these pins. It is left to the system architect to set the SMBus memory map.
Processor 9500 Series, while offset 27h is RESERVED for the Intel Itanium ® Processor 9500 Series. Example: For the Intel® Itanium® processor 9300 series, the 1733 GHz processor will ® ® have a value of 1733. For the Intel Itanium Processor 9500 Series eight core SKU, 0x26 will have a value of 8.
Maximum Intel QuickPath Interconnect Link Transfer Rate ® Offset 2Eh-30h provides maximum operating link transfer rate for the Intel QuickPath Interconnect. A link rate of 4.8 GT/s is expressed as 6 bcd digits in MT/s. Example: 4.8 GT/s = 004800.
Example: A speed of 4.8 GT/s is shown as 004800h. 6.4.4.6 Minimum Memory Transfer Rate Offset 3Ch-3Eh provides minimum “operating” memory transfer rate on the Intel ® Scalable Memory Interconnect. Six 4-bit BCD digits are used to provide the minimum transfer rate in MT/s.
This field is at offset 4Fh through 53h for the substrate layout design. 6.4.6.2 Substrate Revision Software ID This field is at offset 54h for the substrate layout design for the Intel® Itanium® Processor 9300 Series. The field at offset 54h is reserved for the Intel® Itanium® Processor 9500 Series.
Series processors have one TAP per core plus a sysint TAP, this field would be set to 50h ® ® ® for the Intel Itanium Processor 9300 Series processor and 90 for the Intel ® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet...
System Management Bus Interface Itanium ® Processor 9500 Series. Note that even reduced core count Itanium products ® ® (for example, 2-core Intel Itanium Processor 9300 Series) will still have all devices on the TAP chain. 6.4.10 Other Data Addresses 7Dh-7Fh are listed as reserved.
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System Management Bus Interface ® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet...
These transmit clock signals are driven by the processor and are required to be the ® same frequency at both ends but may differ by a fixed phase. An Intel QuickPath Interconnect local port transmit side sends a forwarded clock to the receive side of the remote port and vice-versa, to maintain timing reference at either end of the link.
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Signal Definitions Table 7-1. Signal Definitions for the Intel ® Itanium ® Processor 9300 Series and Intel ® ® Itanium 9500 Series (Sheet 2 of 8) Name Type Description CSI[3:0]R[P/N]Dat[19:0], These input data signals provide means of communication between two ports via CSI[5:4]R[P/N]Dat[9:0] one uni-directional transfer link (In).
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Example: FBD1SBICLKDP0 represents FB-DIMM branch 1, southbound clock output signal of channel D and positive bit of the differential pair. ® ® FBD[0/1]REFSYSCLK[P/N] These signals are no longer used by the Intel Itanium Processor 9300 Series and ® ® Intel Itanium 9500 Series.
0 signal of channel C and positive bit of the differential pair. FBD1NBI[C/D][P/N][13] These signals are spare lanes, and are intended for Reliability, Availability, and ® ® Serviceability (RAS) coverage on the Intel Itanium 9500 Processor Series. These ® ®...
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Itanium ® 9500 Series processors. This clock is driven by the SMBus controller and is asynchronous to ® ® other clocks in the processor. This is an open drain signal. Intel Itanium ® ® Processor 9300 Series and Intel Itanium 9500 Series are Slave only.
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SPDCLK This is a bi-directional clock signal between the processor, DRAM SPD registers and ® external components on the board. This is an open drain signal. The Intel ® Itanium Processor 9300 Series and 9500 Series Processors are Master only; refer ®...
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VCCA. ® ® VCCCACHE This provides power to the Cache on the Intel Itanium 9300 Processor Series. This is on the top of the package and is driven by the Ararat Voltage Regulator. Actual value of the voltage is determined by the settings of VID_VCCCACHE[5:0].
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Signal Definitions Table 7-1. Signal Definitions for the Intel ® Itanium ® Processor 9300 Series and Intel ® ® Itanium 9500 Series (Sheet 8 of 8) Name Type Description VR_THERMTRIP_N This signal is open drain/collector driven by Ararat Voltage Regulator into a pad at the top of the processor package and out through a pin at the bottom of the processor package.
2-13 VCCUNCORE Static and Transient Tolerance for the ® ® Intel Itanium Processor 9500 Series ..............50 ® ® 2-14 VCCUNCORE Load Line for the Intel Itanium Processor 9500 Series ..... 50 ® ® 2-15 VCCCORE Load Line for the Intel Itanium Processor 9500 Series ......51 2-16 VR Sense Point (Representation) .................
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® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet...
2-34 Debug Signal Group DC Specifications ..............56 2-35 PIROM Signal Group DC Specifications ..............56 2-36 Intel® Itanium® Processor 9300 Series VCCCORE (VID_VCCCORE) and VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for Ararat ..58 2-37 Intel® Itanium® Processor 9500 Series VCCCORE (VID_VCCCORE) and VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for Ararat II ..................59...
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