Intel i960 Jx Developer's Manual page 158

Microprocessor
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INSTRUCTION SET REFERENCE
Example:
dcctl g0,g1,g2
Opcode:
dcctl
See Also:
sysctl
DCCTL function 6 stores data-cache sets to a target range in external mem-
Notes:
ory. For any memory location that is cached and also within the target range
for function 6, the corresponding word-valid bit is cleared after function 6
completes to ensure data-cache coherency. Thus,
the state of the cache after it completes, but only the word-valid bits. In all
cases, even when the cache sets to store to external memory overlap the cache
sets that map the target range in external memory, DCCTL function 6 always
returns the state of the cache as it existed when the DCCTL was issued.
This instruction is implemented on the 80960Rx, 80960Hx and 80960Jx pro-
cessor families only, and may or may not be implemented on future i960 pro-
cessors.
6-46
# g0 = 6, g1 = 0x10000000,
# g2 = 0x001F0001
# Store the status of D-cache
# sets 1-0x1F to memory starting
# at 0x10000000.
65CH
REG
dcctl
function 6 can alter

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