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CHAPTER 4
CACHE AND ON-CHIP DATA RAM
This chapter describes the structure and user configuration of all forms of on-chip storage,
including caches (data, local register and instruction) and data RAM.
4
4.1
INTERNAL DATA RAM
Internal data RAM is mapped to the lower 1 Kbyte (0 to 03FFH) of the address space. Loads and
stores with target addresses in internal data RAM operate directly on the internal data RAM; no
external bus activity is generated. Data RAM allows time-critical data storage and retrieval without
dependence on external bus performance. Only data accesses are allowed to the internal data
RAM; instructions cannot be fetched from the internal data RAM. Instruction fetches directed to
the data RAM cause an OPERATION.UNIMPLEMENTED fault to occur.
Internal data RAM locations are never cached in the data cache. Logical Memory Template bits
controlling caching are ignored for data RAM accesses. However, the byte ordering of the internal
data RAM is controlled by the byte-endian control bit in the DLMCON register.
Some internal data RAM locations are reserved for functions other than general data storage. The
first 64 bytes of data RAM may be used to cache interrupt vectors, which reduces latency for these
interrupts. The word at location 0000H is always reserved for the cached NMI vector. With the
exception of the cached NMI vector, other reserved portions of the data RAM can be used for data
storage when the alternate function is not used. All locations of the internal data RAM can be read
in both supervisor and user mode.
The first 64 bytes (0000H to 003FH) of internal RAM are always user-mode write-protected. This
portion of data RAM can be read while executing in user or supervisor mode; however, it can be only
modified in supervisor mode. This area can also be write-protected from supervisor mode writes by
setting the BCON.sirp bit. See
section 13.4.1, "Bus Control (BCON) Register" (pg.
13-6).
Protecting this portion of the data RAM from user and supervisor writes preserves the interrupt
vectors that may be cached there. See
section 11.9.2.1, "Vector Caching Option" (pg.
11-35).
4-1
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