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Intel i960 Series Manuals
Manuals and User Guides for Intel i960 Series. We have
3
Intel i960 Series manuals available for free PDF download: User Manual, Design Manual
Intel i960 Series User Manual (347 pages)
Processor compiler
Brand:
Intel
| Category:
Processor
| Size: 0 MB
Table of Contents
Table of Contents
3
Chapter 1 The CTOOLS Compilation System
12
Features
12
Compatibility and Conformance to Standards
13
Compiler Limits
14
About this Manual
15
Chapter Descriptions
15
Audience Description
17
Licensing and Copyrights
17
UNIX and Windows Conventions
17
Customer Service
18
Where Do You Go from here
18
Chapter 2 Gcc960 Compiler Driver
19
Controlling the Compilation System with Gcc960
19
Invoking the Compiler with Gcc960
20
Gcc960 Sample Command Lines
21
Gcc960 Linker Options
23
Gcc960 and Predefined Macros
24
Linker Options Accepted by Gcc960
24
Gcc960 and File Use
26
Input Files
26
Include Files
27
Output Files
27
Intermediate Inputs and Outputs
28
GLD Files
29
Gcc960 Options
31
Option Arguments and Syntax
33
Gcc960 Option Summary
33
Mcore Supported Architectures
59
Chapter 3 Ic960 Compiler Driver
77
Controlling the Compilation System with Ic960
77
Invoking the Compiler with Ic960
78
Ic960 Sample Command Lines
79
Ic960 Linker Options
80
Linker Options Accepted by Ic960
81
Ic960 and Predefined Macros
82
Ic960 and Environment Variables
84
Ic960 and File Use
87
Input Files
87
Include Files
87
Temporary Files
88
Output Files
88
Intermediate Inputs and Outputs
89
Ic960 Options
91
Option Arguments and Syntax
93
Ic960 Option Summary
93
Gcore Supported Architecures
113
Stop-After Option Phases and Output
135
Introduction
154
About Profiling
155
Chapter 4 Program-Wide Analysis and Optimization
156
Compiling for Program-Wide Optimization with the Fdb Option
156
Selecting Modules for Optimization with Substitution Specifications
157
Profiling Your Program
158
Building Self-Contained Profiles with Gmpf960
159
Using Profiles During Global Decision Making and Optimization with -Gcdm,Iprof
160
Adapting Makefiles for Program-Wide Optimization
161
Using Makefiles with Program-Wide Optimizations for Common Development Tasks
163
Runtime Support for Profile Collection
168
Chapter 5 Profile Data Merging and Data Format (Gmpf960)
169
Merging Profile Data
169
Gmpf960 Invocation
170
Profile Format Specification
172
Profile Data Structures
172
Default.pf File Format
172
Creating a Runtime Report with Gmpf960
174
Chapter 6 Gcdm Decision Maker Option
177
Gcdm Option Syntax
177
Gcdm Option Arguments
177
Gcdm Option Arguments
178
Substitution Controls
178
Whole-Program Optimization Option (Category 1)
179
Module-Local Optimization Options (Category 2)
179
Miscellaneous Substitution Options (Category 3)
181
External Reference Controls
183
Input Profile Control
184
Dryrun Control
185
Module-Set Specification
189
Chapter 7 Language Implementation
190
Data Representation
190
Scalar Data Types
191
Aggregates
193
Natural Alignment
197
User-Constrained Alignment
198
Optimal Natural Alignment of Std_Struct
201
Backward-Compatible Natural Alignment of Std_Struct
202
Other Type Keywords
203
Definitions
204
Parameter Assignment to Registers
206
Return Values
207
Object Module Section Use
208
Pragmas
209
Pragma Align [For Ic960, or for Gcc960 with Ic960 Option]
211
Pragma Cave
215
Pragma Compress
219
Pragma I960_Align [For Gcc960 and Ic960]
220
Pragma Interrupt
221
Pragma Isr
223
Pragma Pack
224
Example Offset Values
225
Pragma Pure
226
Pragma Section
227
Language Extensions
228
Statements and Declarations Inside of Expressions
229
Referring to a Type with Typeof
230
Generalized Lvalues
231
Conditional Expressions with Omitted Middle Operands
233
Non-Lvalue Arrays Can Have Subscripts
234
Non-Constant Initializers
235
Declaring Attributes of Functions
236
Inquiring about Alignment
237
Controlling Names Used in Assembly Code
239
Specifying Registers for Local Variables
240
Inline Assembly Language
241
Asm Statements
242
Asm Functions
259
Argument Category to Parameter Class Matching and Coercion
264
Return Value Class Matching
264
C Data Types and Asm Classes
267
Chapter 8 Gcc960/Ic960 Compatibility
276
Char and Short Parameters
276
Architecture Macros and Compatibility
277
Char Types
277
Pragma Align
278
Position-Independent Code and Data
279
Chapter 9 Position Independence and Reentrancy
280
Position-Independent Code
280
Example: Position-Independent ROM Code
281
Memory for Hypothetical Position-Independent Application
282
Guidelines for Writing Relocatable Programs
283
Reentrant Functions
284
Chapter 10 Initializing the Execution Environment
285
Startup Code
285
RAM-Based Initialization
288
Linker Configuration Files
289
RAM-Based Configuration File
290
Chapter 11 Optimization
291
Optimization Categories and Mechanisms
291
Optimizations and O Level Settings
292
Constants and Expression Evaluation
293
Constant Expression Evaluation (Constant Folding)
294
Dead-Code Elimination
295
Constant Propagation
296
Calls, Jumps, and Branches
299
Branch Prediction
300
Identification of Leaf Functions
301
Tail-Call Elimination
302
Loop Optimizations
304
Loop Unrolling
305
Variable Shadowing
306
Local Variable Promotion
307
Instruction Selection and Sequencing
308
Specialized-Instruction Selection
310
Superblock Formation
311
Profile-Based Branch-Prediction Bit Setting
312
Chapter 12 Caveats
313
Aliasing Assumptions
313
Alignment Assumptions
315
Volatile Objects
316
Known Problems Using the Compiler
318
Longjmp and Volatile Data
319
C Version Incompatibilities
320
Combining Long with Typedef Names
321
Flagging Unterminated Character Constants
322
C Interrupt Service Routine Failures
323
Preventing Structure Padding
324
Breakpoints Inside Interrupt Handlers
327
Chapter 13 Messages
329
Messages on the Standard Error Device
329
Messages in the Listing File
330
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Intel i960 Series Design Manual (102 pages)
RM/RN I/O Processor
Brand:
Intel
| Category:
Computer Hardware
| Size: 1 MB
Table of Contents
Table of Contents
3
Revision History
8
1 Introduction
9
2 Intel ® 80960RM/RN Processor Ball Map
9
Intel ® 80960RM/RN Processor PBGA Signal Ball Map
10
L H-PBGA Diagram (Bottom View)
10
3 Routing Guidelines
11
Trace Length Limits
11
Examples of Stubless and Short Stub Traces
11
4 Intel ® 80960RM/RN Processor Memory Subsystem
12
ROM, SRAM, or Flash Guidelines
12
Flash Interface Signals
12
Layout Guidelines
13
Wait State Profiles
13
Mbyte Flash Memory System
13
ROM, SRAM, or Flash Wait State Profile Programming
13
SDRAM Guidelines
14
SDRAM Interface Signals
14
Layout Guidelines
15
Dual-Bank SDRAM Memory Subsystem
15
Drive Strength Programmability Options
16
SDRAM DIMM Layout Topology #1
17
SDRAM DIMM Layout Topology #2
17
Address and Control Topology for Two Discrete SDRAM Devices
18
Address and Control Topology for Four or more Discrete SDRAM Devices
18
Data and DQM Topology for Discrete SDRAM Devices
19
SDRAM Clocking and Clock Buffer Specifications
20
Clocking for a Dual-Bank SDRAM DIMM
20
DCLKIN Routing and Loading Requirements
21
Clock Routing for a Two Device SDRAM Subsystem
22
SDRAM Clock Buffer Information
22
SDRAM Power Failure Guidelines
23
System Assumptions
23
External Logic Required for Power Failure
23
External Power Failure State Machine
23
External Power Failure Logic in the System
24
5 Interrupt Routing
25
Intel ® 80960RM/RN Processor Implementation on a Motherboard
25
Intel ® 80960RM/RN Processor Implementation on an Add-In Card
26
Example Secondary PCI Connector Interrupt Routing
26
6 Clocking Guidelines
27
Layout Guidelines for Add-In Cards
27
PCI Add-In Card Example Configuration
27
Layout Guidelines for Motherboards
28
Motherboard Example Configuration
28
Clock Vendors
29
Low Skew Clock Buffer Information
29
7 Intel ® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors
30
Memory Controller, Core and JTAG Signals
30
I 2 C Bus Signals
30
PCI Signals
30
PCI Signals
31
8 Intel ® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors
32
Memory Controller, Core and JTAG Signals
32
I 2 C Bus Signals
32
9 Intel ® 80960RM/RN Processor 5 V and 3.3 V Design Considerations
34
Providing 3.3 V in a 5 V System
34
Creating a Power "Island
35
Choosing a Power Source
36
Power Supply Circuit
36
Recommended Power Supply Connection Layout
36
PCI Adapter Card Power Source
37
VCC5REF Pin Requirement
37
Diff )
37
Vcc5Ref
37
Vdiff
37
Pullups and Pulldown Resistors
38
Fail
39
Recommended FAIL# Circuit
39
10 Processor Power Supply Decoupling
40
High Frequency Decoupling
40
Bulk Decoupling Capacitance
41
High-Frequency Capacitor Values and Layout
41
11 Intel 80960RM/RN Processor Based Reference Design
42
12 Debug Connector Recommendations
43
PBGA Sockets and Headers
43
L PBGA Socket
44
Logic Analyzer Connectivity
45
Packard-Hughes Direct Mount (Flex Tape) Interposer - Top View
46
Packard-Hughes Direct Mount (Flex Tape) Interposer - Side View
46
Flex Tape Interposer Application (Add-In Card)
47
Flex Tape Interposer (Top View)
47
Flex Tape Interposer (Side View)
47
JTAG Connector and Test Interface
48
Intel ® I960 ® RM/RN I/O Processor JTAG Emulator
48
Intel RM/RN I/O Processor JTAG Emulator
48
Intel ® I960 ® RM/RN I/O Processor Target Debug Interface Connector
48
RM/RN I/O Processor Debug Connector Wiring
49
Connecting the Emulator to the Target
50
I960 ® RM/RN I/O Processor with PC-1149.1/100F (Cable P/N AS01090025-Ax)
50
Other Tools
51
I960 ® RM/RN I/O Processor with PCMCIA-1149.1 (Cable P/N AS01090025-Bx)
51
13 Design for Manufacturability
52
14 Thermal Solutions
53
Thermal Recommendations
53
3-Dimensional View: Processor with Heat Sink Attached
54
PCB Heatsink Hole Dimensions
55
Board Level Keep out Areas
56
Clearances of PCI Board and Components
57
Heat Sink Information
58
Socket Information
58
Socket-Header Vendor
58
Burn-In Socket Vendor
58
Shipping Tray Vendor
59
Logic Analyzer Interposer Vendor
59
JTAG Emulator Vendor
59
15 References
60
Related Documents
60
Electronic Information
60
Related Documentation
60
Intel RM I/O Processor Schematics
61
Decoupling and 3.3 V Power Schematic
62
Primary PCI Interface Schematic
63
Memory Controller Schematic
64
Flash ROM, UART and Leds Schematic
65
Logic Analyzer I/F Schematic
66
SDRAM 168-Pin DIMM Schematic
67
Secondary PCI/80960 Core Schematic
68
Secondary PCI Bus 1/2 Schematic
69
Secondary PCI Bus 3/4 Schematic
70
Battery Monitor Schematic
71
Intel IQ80960RM Board Bill of Material
72
Intel ® IQ80960RM Bill of Materials
72
Intel RN I/O Processor Schematics
76
Decoupling and 3.3 V Power Schematic
77
Primary PCI Interface Schematic
78
Memory Controller Schematic
79
Flash ROM, UART and Leds Schematic
80
Logic Analyzer I/F Schematic
81
SDRAM 168-Pin DIMM Schematic
82
Secondary PCI/80960 Core Schematic
83
Secondary PCI Bus 1/2 Schematic
84
Secondary PCI Bus 3/4 Schematic
85
SPCI Pull-Ups Schematic
86
Battery/Monitor Schematic
87
Intel IQ80960RN Board Bill of Material
88
Intel ® IQ80960RN Bill of Materials
88
Intel IQ80960RM/RN SDRAM Battery Backup PLD Equations
92
Intel 80960RM/RN Processor PBGA Signal Ball Map
93
Intel i960 Series User Manual (102 pages)
for Cyclone and PCI-SDK Evaluation Platforms
Brand:
Intel
| Category:
Computer Hardware
| Size: 0 MB
Table of Contents
Table of Contents
3
Chapter 1 Introduction
18
Advantages and Features
18
About this Manual
18
Notation Conventions
19
Technical Support, Schematics and Pld Equations
19
Additional Information
20
Chapter 2 Getting Started
21
Pre-Installation Considerations
23
Software Development Tools
23
MON960 Debug Monitor
23
Host Communications
24
Terminal Emulation Method
24
Host Debugger Interface Library (HDIL) Method
24
Source Level Debugger
24
Power Requirements
24
Software Installation
25
Installing Software Development Tools
25
Hardware Installation
25
Verify Cyclone EP Is Functional
25
Creating and Downloading the Example Program
26
MONDB.EXE-To-Cyclone EP Communication Support
26
Terminal Emulation-To-Cyclone EP Communication Support
28
Chapter 3 Hardware Reference
29
Connectors, Switches and Leds
31
Table 3-1 External Connectors and Leds
32
Cpu Modules
33
CPU Module Installation
33
CPU Module Clock Frequencies
33
Table 3-2 CPU Module Frequency Switch Settings
33
I960 Jx/Hx CPU Counter/Timers
34
CPU Module VPP Switch
34
Cpu Memory Map
34
Table 3-3 I960 Jx/Hx CPU Clock Rates
34
Interleaved Dram
35
DRAM Performance
35
Upgrading SIMM DRAM
36
Table 3-4 DRAM Access Times
36
Flash Memory
37
Swaprom Switch
37
Table 3-5 DRAM SIMM Configurations
37
Table 3-6 Flash ROM Addresses
37
Interrupts
38
Table 3-7 Interrupt Sources
38
Table 3-8 80960Sx and Kx Interrupt Sources
38
Console Serial Port
39
Table 3-9 80960Sx and Kx Interrupt Switch Settings
39
Table 3-10 UART Register Addresses
39
Parallel Port
40
Parallel Port Bit Assignments
40
Table 3-11 Parallel Port Addresses
40
Table 3-12 Parallel Port Status Register Bit Assignments
40
Z8536 Counter I/O Unit (Cio)
41
Counter/Timers
41
Table 3-13 Parallel Port Control Register Bit Assignments
41
Table 3-14 CIO Register Address
41
CIO Port a
42
CIO Port B
43
CIO Port C
44
Non-Volatile Parameter Memory
44
Squall II Module Interface
44
Table 3-17 Available Squall II Modules
45
Table 3-18 Squall Module Compatibility at Maximum CPU Clock Speed (33 Mhz)
45
PLX PCI 9060 INTERFACE (PCI-SDK Platform Only)
46
PCI 9060 Configuration
46
Accessing Configuration Registers
47
PCI-To-Local Configuration
48
Table 3-19 Local Configuration Registers
48
RAM Region Configuration
49
Table 3-20 PCI Configuration Registers
49
Table 3-21 Memory Region 0 Settings
50
Table 3-22 Local Address Space 0 Range Register
50
Table 3-23 Local Address Space 0 Local Base Address (Re-Map) Register Description
50
Table 3-24 Local Bus Region Descriptor for PCI-To-Local Access Register Description
51
Expansion ROM Region Configuration
52
Memory Region Configuration Examples
52
Table 3-25 ROM Region Settings
52
Table 3-26 Local Expansion ROM Local Base Address (Re-Map) and Breqo Register Description
53
Table 3-27 Local Expansion ROM Range Register Description
53
Local-To-PCI Configuration
54
Table 3-28 Local Range Register for Direct Master-To-PCI Description
55
Table 3-29 PCI Base Address (Re-Map) Register for Direct Master-To-PCI Description
55
Table 3-30 Local Bus Base Address Register for Direct Master-To-PCI Memory
56
Table 3-31 Local Base Address for Direct Master-To-PCI IO/CFG Register
56
Deadlock Configuration
57
Table 3-32 PCI Configuration Address Register for Direct Master-To-PCI IO/CFG
57
Signalling Init Done
58
PCI Interrupts
58
Local PCI Interrupts
59
Table 3-33 Interrupt Control/Status
59
Mailbox Registers and Doorbell Interrupts
61
Using the Mailbox Registers
61
Generating Doorbell Interrupts
61
Receiving Doorbell Interrupts
61
DMA Programming
62
DMA Non-Chaining Mode
62
DMA Chaining Mode
63
DMA Interrupts
64
Chapter 4 Theory of Operation
65
Functional Overview
67
Clock Generation
67
Power Monitor and Reset
68
I/O Interface
68
Functional Blocks
69
I/O Control Timing
69
Data Path
70
Parallel Port
71
Serial Port
72
Dram Subsystem
72
Page Mode DRAM SIMM Review
72
Bank Interleaving
73
Wait State Performance
73
DRAM Controller Implementation
74
Table 4-1 DRAM Profiles
74
CAS Generation
76
Refresh Generation
76
Chapter 5 Squall II Module Interface
77
Physical Attributes
79
Power Requirements
81
Squall II Module Serial EEPROM
81
Table 5-1 Power Supply
81
Squall II Module Signal Definitions
82
Squall Module Signal Descriptions
83
Table 5-2 Pin Description Nomenclature
83
Table 5-3 Squall Module Signal Descriptions
83
Squall II Module Timing
86
Squall II Module Slave Timing
86
Table 5-4 Squall II Module Slave Timing
87
Squall II Module Master Timing
90
Table 5-5 Squall II Module Master Timing
91
Squall II Module Connector
95
Table 5-6 Squall II Module Pin Assignments
95
Squall II Module Signal Loading and Logic Selection
96
Squall II Module Clock Termination
96
Table 5-7 Squall II Module Signal Loading
96
Appendix A
97
Parts List
97
Table A-1 Cyclone EP/PCI-SDK Platform Bill of Materials
99
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