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Intel i960 Jx manual available for free PDF download: Developer's Manual
Intel i960 Jx Developer's Manual (578 pages)
Microprocessor
Brand:
Intel
| Category:
Computer Hardware
| Size: 3.42 MB
Table of Contents
Table of Contents
3
CHAPTER 1 Product Features
28
Instruction Cache
28
Data Cache
28
On-Chip (Internal) Data RAM
28
Local Register Cache
29
Interrupt Controller
29
Timer Support
30
Memory-Mapped Control Registers (MMR)
30
CHAPTER 14 External Bus
30
Complete Fault Handling and Debug Capabilities
31
About this Manual
31
Notation and Terminology
32
Reserved and Preserved
32
Register Names
33
Representing Numbers
33
Specifying Bit and Signal Values
33
Related Documents
34
Table 1-1. Register Terminology Conventions
34
Data Types
37
Figure 2-1. Data Types and Ranges
37
Chapter 2
38
Integers
38
Ordinals
38
Bits and Bit Fields
39
Triple- and Quad-Words
39
Register Data Alignment
39
Literals
40
Bit and Byte Ordering in Memory
40
Bit Ordering
40
Byte Ordering
40
Table 2-1. Memory Contents for Little and Big Endian Example
41
Table 2-2. Byte Ordering for Little and Big Endian Accesses
41
Figure 2-2. Data Placement in Registers
42
Table 2-3. Memory Addressing Modes
42
Absolute
43
Register Indirect
43
Index with Displacement
44
IP with Displacement
44
Addressing Mode Examples
44
Overview
49
Chapter 3 Registers and Literals as Instruction Operands
49
Figure 3-1. I960 ® Jx Processor Programming Environment Elements
50
Global Registers
50
Local Registers
51
Table 3-1. Registers and Literals Used as Instruction Operands
51
Literals
52
Register and Literal Addressing and Alignment
52
Register Scoreboarding
52
Table 3-2. Allowable Register Operands
53
Memory-Mapped Control Registers
54
Memory-Mapped Registers (MMR)
54
Restrictions on Instructions that Access Memory-Mapped Registers
54
Access Faults
55
Table 3-3. Access Types
56
Table 3-4. Supervisor Space Family Registers
57
Architecturally Defined Data Structures
59
Table 3-5. User Space Family Registers and Tables
59
Table 3-6. Data Structure Descriptions
60
Figure 3-2. Memory Address Space
61
Memory Requirements
62
Byte, Word and Bit Addressing
63
Data and Instruction Alignment in the Address Space
63
Table 3-7. Alignment of Data Structures in the Address Space
63
Chapter 4
64
Internal Data RAM
64
Instruction Cache
64
Data Cache
65
Local Register Cache
65
Processor-State Registers
65
Instruction Pointer (IP) Register
65
Figure 3-3. Arithmetic Controls (AC) Register
66
Initializing and Modifying the AC Register
66
Condition Code (Ac.CC)
67
Table 3-10. Condition Codes for Carry out and Overflow
67
Table 3-8. Condition Codes for True or False Conditions
67
Table 3-9. Condition Codes for Equality and Inequality Conditions
67
Figure 3-4. Process Controls (PC) Register
69
Initializing and Modifying the PC Register
70
Trace Controls (TC) Register
71
User-Supervisor Protection Model
71
Supervisor Mode Resources
71
Using the User-Supervisor Protection Model
72
Internal Data Ram
75
Figure 4-1. Internal Data RAM and Register Cache
76
Local Register Cache
76
Big Endian Accesses to Internal Ram and Data Cache
78
Appendix A Instruction Cache
78
Enabling and Disabling the Instruction Cache
78
Operation While the Instruction Cache Is Disabled
79
Loading and Locking Instructions in the Instruction Cache
79
Instruction Cache Visibility
79
Instruction Cache Coherency
79
Enabling and Disabling the Data Cache
80
Multi-Word Data Accesses that Partially Hit the Data Cache
81
Data Cache Fill Policy
82
Data Cache Write Policy
82
Data Cache Coherency and Non-Cacheable Accesses
83
External I/O and Bus Masters and Cache Coherency
84
Data Cache Visibility
84
Instruction Formats
87
Chapter 5
87
Assembly Language Format
87
Table 5-1. Instruction Encoding Formats
88
Instruction Operands
89
Instruction Groups
90
Table 5-2. 80960Jx Instruction Set
90
Data Movement
91
Load and Store Instructions
91
Move
92
Load Address
92
Select Conditional
92
Table 5-3. Arithmetic Operations
93
Add, Subtract, Multiply, Divide, Conditional Add, Conditional Subtract
94
Remainder and Modulo
94
Shift, Rotate and Extended Shift
95
Extended Arithmetic
96
Logical
96
Bit, Bit Field and Byte Operations
97
Bit Operations
97
Bit Field Operations
97
Comparison
98
Compare and Conditional Compare
98
Compare and Increment or Decrement
99
Test Condition Codes
99
Branch
100
Unconditional Branch
100
Conditional Branch
101
Compare and Branch
101
Call/Return
102
Faults
103
Atomic Instructions
104
Debug
104
Processor Management
105
Performance Optimization
106
Instruction Optimizations
106
Load / Store Execution Model
106
Compare Operations
106
Microcoded Instructions
107
Multiply-Divide Unit Instructions
107
Multi-Cycle Register Operations
107
Simple Control Transfer
108
Memory Instructions
108
Unaligned Memory Accesses
109
Miscellaneous Optimizations
109
Masking of Integer Overflow
109
Avoid Using PFP, SP, R3 as Destinations for MDU Instructions
109
Execute in Imprecise Fault Mode
110
Chapter 6 Notation
113
Alphabetic Reference
114
Mnemonic
114
Format
114
Description
115
Action
115
Table 6-1. Pseudo-Code Symbol Definitions
116
Table 6-2. Faults Applicable to All Instructions
116
Example
117
Faults
117
Table 6-3. Common Faulting Conditions
117
Opcode and Instruction Format
118
See also
118
Side Effects
118
Notes
118
Instructions
118
Add<CC>
119
Table 6-4. Condition Code Mask Descriptions
119
Table 6-5. Condition Code Mask Descriptions
120
Addc
122
Addi, Addo
123
Alterbit
124
And, Andnot
125
Atadd
126
Atmod
127
Bal, Balx
129
Bbc, Bbs
131
Branch<CC>
133
Bswap
135
CHAPTER 7 Call
136
Calls
137
Callx
139
Chkbit
141
Clrbit
142
Cmpdeci, Cmpdeco
143
Table 6-6. Condition Code Settings
143
Cmpinci, Cmpinco
144
Table 6-7. Condition Code Settings
144
Compare
145
Table 6-8. Condition Code Settings
145
COMPARE and Branch<CC>
147
Table 6-9. Condition Code Mask Descriptions
148
Concmpi, Concmpo
150
Table 6-10. Concmpo Example: Register Ordering and CC
151
Table 6-11. Dcctl Operand Fields
152
Figure 6-1. Dcctl Src1 and Src/Dst Formats
153
Figure 6-4. Icctl Src1 and Src/Dst Formats
171
Table 6-16. ICCTL Status Values and Instruction Cache Parameters
172
Figure 6-5. Store Instruction Cache to Memory Output Format
173
Figure 6-6. I-Cache Set Data, Tag and Valid Bit Formats
174
Intctl
178
Intdis
180
Inten
181
Load
182
Mark
186
Modac
187
Modi
188
Modify
189
Modpc
190
Modtc
192
Move
193
Muli, Mulo
196
Nand
197
Not, Notand
199
Notbit
200
Notor
201
Or, Ornot
202
Remi, Remo
203
Rotate
206
Scanbit
207
Scanbyte
208
Sel<CC>
209
Table 6.17. Condition Code Mask Descriptions
209
Setbit
211
Shift
212
Spanbit
215
Store
216
Subc
220
Sub<CC>
221
Subi, Subo
224
Syncf
225
Figure 6-7. Src1 Operand Interpretation
226
Table 6-18. Sysctl Field Definitions
226
Figure 6-8. Src/Dst Interpretation for Breakpoint Resource Request
227
Table 6-19. Cache Mode Configuration
227
Table 6-20. Condition Code Mask Descriptions
230
Test<CC>
230
Xnor, Xor
232
Call and Return Mechanism
236
Local Registers and the Procedure Stack
236
Figure 7-1. Procedure Stack Structure and Local Registers
237
Local Register and Stack Management
238
Frame Pointer
238
Stack Pointer
238
Considerations When Pushing Data Onto the Stack
238
Considerations When Popping Data off the Stack
239
Previous Frame Pointer
239
Return Type Field
239
Call and Return Action
239
Call Operation
240
Return Operation
241
Return Instruction Pointer
239
Caching Local Register Sets
241
Reserving Local Register Sets for High Priority Interrupts
242
Figure 7-2. Frame Spill
243
Figure 7-3. Frame Fill
244
Mapping Local Registers to the Procedure Stack
245
Modifying the Pfp Register
245
Parameter Passing
246
Local Calls
248
System Calls
249
System Procedure Table
249
Figure 7-4. System Procedure Table
250
Procedure Entries
251
Supervisor Stack Pointer
251
Table 7-1. Encodings of Entry Type Field in System Procedure Table
251
Trace Control Bit
251
System Call to a Local Procedure
252
System Call to a Supervisor Procedure
252
Interrupt and Fault Calls
253
User and Supervisor Stacks
253
Figure 7-5. Previous Frame Pointer Register (PFP) (R0)
254
Returns
254
Branch-And-Link
255
Table 7-2. Encoding of Return Status Field
255
Figure 6-2. Store Data Cache to Memory Output Format
154
Table 6-12. DCCTL Status Values and D-Cache Parameters
154
Figure 6-3. D-Cache Tag and Valid Bit Formats
155
DIVI, Divo
159
Ediv
160
Emul
161
Eshro
162
Extract
163
Fault<CC>
164
Table 6-13. Condition Code Mask Descriptions
164
Flushreg
166
Fmark
167
Halt
168
Table 6-15. Icctl Operand Fields
170
Chapter 8
259
Fault Handling Overview
259
Figure 8-1. Fault-Handling Data Structures
259
Fault Types
261
Fault Table
262
Figure 8-2. Fault Table and Fault Table Entries
263
Stack Used in Fault Handling
264
Fault Record
264
Fault Record Description
265
Figure 8-3. Fault Record
265
Fault Record Location
266
Figure 8-4. Storage of the Fault Record on the Stack
266
Multiple and Parallel Faults
267
Multiple Non-Trace Faults on the same Instruction
267
Multiple Trace Fault Conditions on the same Instruction
267
Multiple Trace and Non-Trace Fault Conditions on the same Instruction
267
Faults on Multiple Instructions Executed in Parallel
268
Fault Record for Parallel Faults
269
Override Faults
269
System Error
270
Fault Handling Procedures
270
Possible Fault Handling Procedure Actions
271
Program Resumption Following a Fault
271
Faults Happening before Instruction Execution
271
Faults Happening During Instruction Execution
272
Faults Happening after Instruction Execution
272
Return Instruction Pointer (RIP)
272
Returning to the Point in the Program Where the Fault Occurred
273
Returning to a Point in the Program Other than Where the Fault Occurred
273
Fault Controls
273
Fault Handling Action
274
Table 8-2. Fault Control Bits and Masks
274
Local Fault Call
275
System-Local Fault Call
275
System-Supervisor Fault Call
275
Faults and Interrupts
276
Precise and Imprecise Faults
277
Asynchronous Faults
277
No Imprecise Faults (Ac.nif) Bit
278
Controlling Fault Precision
278
Fault Reference
279
ARITHMETIC Faults
280
CONSTRAINT Faults
281
OPERATION Faults
282
OVERRIDE Faults
284
PARALLEL Faults
285
PROTECTION Faults
286
TRACE Faults
287
TYPE Faults
290
Chapter 9 Trace Controls
293
Figure 9-1. 80960Jx Trace Controls (TC) Register
294
PC Trace Enable Bit and Trace-Fault-Pending Flag
295
Trace Modes
295
Instruction Trace
295
Branch Trace
296
Call Trace
296
Return Trace
296
Prereturn Trace
296
Supervisor Trace
297
Mark Trace
297
Software Breakpoints
297
Hardware Breakpoints
297
Requesting Modification Rights to Hardware Breakpoint Resources
298
Breakpoint Control Register
299
Table 9-1. Src/Dst Encoding
299
Figure 9-2. Breakpoint Control Register (BPCON)
300
Table 9-2. Configuring the Data Address Breakpoint (DAB) Registers
300
Table 9-3. Programming the Data Address Breakpoint (DAB) Modes
300
Data Address Breakpoint (DAB) Registers
301
Figure 9-3. Data Address Breakpoint (DAB) Register Format
302
Figure 9-4. Instruction Breakpoint (IPB) Register Format
302
Generating a Trace Fault
303
Handling Multiple Trace Events
303
Table 9-4. Instruction Breakpoint Modes
303
Trace Fault Handling Procedure
304
Tracing and Interrupt Procedures
304
Tracing on Calls and Returns
304
Table 9-5. Tracing on Explicit Call
305
Table 9-6. Tracing on Implicit Call
306
Table 9-7. Tracing on Return from Explicit Call
307
Table 9-8. Tracing on Return from Fault
307
Tracing on Return from Implicit Call: Fault Case
307
Table 9-9. Tracing on Return from Interrupt
308
Tracing on Return from Implicit Call: Interrupt Case
308
Figure 10-1. Timer Functional Diagram
311
Table 10-1. Timer Performance Ranges
312
Table 10-2. Timer Registers
312
Figure 10-2. Timer Mode Register (TMR0, TMR1)
313
Timer Mode Registers (TMR0, TMR1)
313
Chapter 10
314
Bit 0 - Terminal Count Status Bit (Tmrx.tc)
314
Bit 1 - Timer Enable (Tmrx.enable)
314
Bit 2 - Timer Auto Reload Enable (Tmrx.reload)
315
Bit 3 - Timer Register Supervisor Read/Write Control (Tmrx.sup)
315
Bits 4, 5 - Timer Input Clock Select (Tmrx.csel1:0)
316
Timer Count Register (TCR0, TCR1)
316
Figure 10-3. Timer Count Register (TCR0, TCR1)
316
Table 10-3. Timer Input Clock (TCLOCK) Frequency Selection
316
Timer Reload Register (TRR0, TRR1)
317
Timer Operation
317
Basic Timer Operation
317
Figure 10-4. Timer Reload Register (TRR0, TRR1)
317
Table 10-4. Timer Mode Register Control Bit Summary
318
Load/Store Access Latency for Timer Registers
319
Table 10-5. Timer Responses to Register Bit Settings
319
Timer Interrupts
321
Powerup/Reset Initialization
321
Table 10-6. Timer Powerup Mode Settings
321
Uncommon Tcrx and Trrx Conditions
322
Table 10-7. Uncommon Tmrx Control Bit Settings
322
Timer State Diagram
323
Figure 10-5. Timer Unit State Diagram
323
Overview
327
The I960 ® Jx Processor Interrupt Controller
328
Figure 11-1. Interrupt Handling Data Structures
328
Chapter 11
329
Software Requirements for Interrupt Handling
329
Interrupt Priority
329
Figure 11-2. Interrupt Table
330
Pending Interrupts
331
Vector Entries
331
Caching Portions of the Interrupt Table
332
Figure 11-3. Storage of an Interrupt Record on the Interrupt Stack
333
Interrupt Stack and Interrupt Record
333
Managing Interrupt Requests
334
External Interrupts
334
Non-Maskable Interrupt (NMI)
334
Software Interrupts
335
Timer Interrupts
335
Posting Interrupts
335
Posting Software Interrupts Via Sysctl
335
Posting Software Interrupts Directly in the Interrupt Table
337
Posting External Interrupts
337
Posting Hardware Interrupts
337
Resolving Interrupt Priority
337
Sampling Pending Interrupts in the Interrupt Table
338
Interrupt Controller Modes
340
Figure 11-4. Dedicated Mode
340
Figure 11-5. Expanded Mode
341
Figure 11-6. Implementation of Expanded Mode Sources
342
Mixed Mode
343
Saving the Interrupt Mask
343
External Interface Description
344
Pin Descriptions
344
Interrupt Detection Options
345
Figure 11-7. Interrupt Sampling
346
Memory-Mapped Control Registers
347
Table 11-1. Interrupt Control Registers Memory-Mapped Addresses
347
Interrupt Control Register (ICON)
348
Figure 11-8. Interrupt Control (ICON) Register
348
Interrupt Mapping Registers (IMAP0-IMAP2)
349
Figure 11-9. Interrupt Mapping (IMAP0-IMAP2) Registers
350
Figure 11-10. Interrupt Pending (IPND) Register
351
Figure 11-11. Interrupt Mask (IMSK) Registers
352
Interrupt Controller Register Access Requirements
353
Default and Reset Register Values
354
Interrupt Operation Sequence
354
Figure 11-12. Interrupt Controller
356
Interrupt Service Routines
357
Setting up the Interrupt Controller
357
Interrupt Context Switch
358
Servicing an Interrupt from Executing State
358
Servicing an Interrupt from Interrupted State
359
Optimizing Interrupt Performance
359
Figure 11-13. Interrupt Service Flowchart
360
Features to Improve Interrupt Performance
361
Vector Caching Option
361
Caching Interrupt Routines and Reserving Register Frames
362
Caching the Interrupt Stack
362
Table 11-2. Location of Cached Vectors in Internal RAM
362
Table 11-3. Base Interrupt Latency
363
Interrupt Service Latency
361
Maximum Interrupt Latency
364
Table 11-4. Worst-Case Interrupt Latency Controlled by Divo to Destination R15
364
Table 11-5. Worst-Case Interrupt Latency Controlled by Divo to Destination R3
365
Table 11-6. Worst-Case Interrupt Latency Controlled by Calls
365
Table 11-7. Worst-Case Interrupt Latency When Delivering a Software Interrupt
366
Table 11-8. Worst-Case Interrupt Latency Controlled by Flushreg of One Stack Frame
367
Avoiding Certain Destinations for MDU Operations
368
Masking Integer Overflow Faults for Syncf
368
Overview
371
Initialization
372
Figure 12-1. Processor Initialization Flow
372
Chapter 12
373
Reset State Operation
373
Figure 12-2. Cold Reset Waveform
374
Table 12-1. Reset States
375
Table 12-2. Register Values after Reset
375
Self Test Function (STEST, FAIL)
376
The STEST Pin
377
External Bus Confidence Test
377
The Fail Pin (FAIL)
377
IMI Alignment Check and System Error
378
FAIL Code
378
Figure 12-3. FAIL Sequence
378
Architecturally Reserved Memory Space
379
Table 12-3. Fail Codes for bist (Bit 7 = 1)
379
Table 12-4. Remaining Fail Codes (Bit 7 = 0)
379
Initial Memory Image (IMI)
380
Figure 12-4. Initial Memory Image (IMI) and Process Control Block (PRCB)
382
Table 12-5. Initialization Boot Record
383
Figure 12-5. PMCON14_15 Register Bit Description in IBR
385
Process Control Block (PRCB)
386
Table 12-6. PRCB Configuration
386
Figure 12-6. Process Control Block Configuration Words
387
Process PRCB Flow
388
AC Initial Image
389
Fault Configuration Word
389
Instruction Cache Configuration Word
389
Register Cache Configuration Word
389
Control Table
390
Figure 12-7. Control Table
391
Device Identification on Reset
392
Reinitializing and Relocating Data Structures
392
Figure 12-8. IEEE 1149.1 Device Identification Register
392
Startup Code Example
393
System Requirements
404
Input Clock (CLKIN)
404
Power and Ground Planes
405
Decoupling Capacitors
406
I/O Pin Characteristics
406
Figure 12-10. Reducing Characteristic Impedance
406
Output Pins
407
Table 12-7. Input Pins
407
High Frequency Design Considerations
408
Line Termination
408
Latchup
409
Figure 12-11. Series Termination
409
Figure 12-12. AC Termination
409
Interference
410
Figure 12-13. Avoid Closed-Loop Signal Paths
411
CHAPTER 13 Memory Attributes
415
Physical Memory Attributes
415
Logical Memory Attributes
416
Figure 13-1. PMCON and LMCON Example
416
Differences with Previous I960 Processors
417
Programming the Physical Memory Attributes (PMCON Registers)
418
Table 13-1. PMCON Address Mapping
418
Bus Width
419
Physical Memory Attributes at Initialization
419
Figure 13-2. PMCON Register Bit Description
419
Bus Control (BCON) Register
420
Figure 13-3. Bus Control Register (BCON)
420
Boundary Conditions for Physical Memory Regions
421
Internal Memory Locations
421
Bus Transactions Across Region Boundaries
421
Modifying the PMCON Registers
421
Programming the Logical Memory Attributes
422
Figure 13-4. Logical Memory Template Starting Address Registers (LMADR0-1)
422
Figure 13-5. Logical Memory Template Mask Registers (LMMR0-1)
423
Figure 13-6. Default Logical Memory Configuration Register (DLMCON)
424
Defining the Effective Range of a Logical Data Template
425
Data Caching Enable
426
Enabling the Logical Memory Template
426
Selecting the Byte Order
426
Boundary Conditions for Logical Memory Templates
427
Initialization
427
Internal Memory Locations
427
Overlapping Logical Data Template Ranges
427
Table 13-2. DLMCON Values at Reset
427
Accesses Across LMT Boundaries
428
Modifying the LMT Registers
428
Dynamic Byte Order Changing
428
Bus Operation
431
Overview
431
Basic Bus States
432
Figure 14.1. Bus States with Arbitration
433
Bus Signal Types
434
Clock Signal
434
Address/Data Signal Definitions
434
Control/Status Signal Definitions
434
Table 14-1. Summary of I960 Jx Processor Bus Signals
435
Bus Accesses
436
Bus Width
437
Figure 14-2. Data Width and Byte Encodings
437
Table 14-2. 8-Bit Bus Width Byte Enable Encodings
438
Table 14-3. 16-Bit Bus Width Byte Enable Encodings
438
Table 14-4. 32-Bit Bus Width Byte Enable Encodings
438
Basic Bus Accesses
439
Figure 14-3. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
440
Burst Transactions
441
Figure 14-4. 32-Bit Wide Data Bus Bursts
442
Figure 14-5. 16-Bit Wide Data Bus Bursts
442
Figure 14-6. 8-Bit Wide Data Bus Bursts
443
Figure 14-7. Unaligned Write Transaction
444
Figure 14-8. Burst Read and Write Transactions W/O Wait States, 32-Bit Bus
445
Figure 14-9. Burst Read and Write Transactions W/O Wait States, 8-Bit Bus
446
Wait States
447
Figure 14-10. Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit Bus
448
Recovery States
449
Figure 14-11. Burst Read/Write Transactions with 1,0 Wait States - Extra Tr State on Read, 16-Bit Bus
450
Figure 14-12. Burst Read/Write Transactions with 1,0 Wait States, Extra Tr State
451
Bus and Control Signals During Recovery and Idle States
452
Data Alignment
452
Table 14-5. Natural Boundaries for Load and Store Accesses
453
Table 14-6. Summary of Byte Load and Store Accesses
453
Table 14-7. Summary of Short Word Load and Store Accesses
453
Table 14-8. Summary of N-Word Load and Store Accesses (N = 1, 2, 3, 4)
454
Figure 14-13. Summary of Aligned and Unaligned Accesses (32-Bit Bus)
455
Figure 14-14. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)
456
Figure 14-15. Accesses Generated by Double Word Read Bus Request, Misaligned One Byte from Quad Word Boundary, 32-Bit Bus, Little Endian
457
Byte Ordering and Bus Accesses
458
Table 14-9. Byte Ordering on Bus Transfers, Word Data Type
458
Figure 14-16. Multi-Word Access to Big-Endian Memory Space
459
Table 14-10. Byte Ordering on Bus Transfers, Short-Word Data Type
459
Table 14-11. Byte Ordering on Bus Transfers, Byte Data Type
459
Atomic Bus Transactions
460
Bus Arbitration
461
Figure 14-17. the LOCK Signal
461
HOLD/HOLDA Protocol
462
BSTAT Signal
463
Figure 14-18. Arbitration Timing Diagram for a Bus Master
463
Bus Applications
464
System Block Diagrams
464
Figure 14-19. Generalized 80960Jx System with 80960 Local Bus
465
Figure 14-20. Generalized 80960Jx System with 80960 Local Bus and Backplane Bus
465
Figure 14-21. 80960Jx System with 80960 Local Bus, PCI Local Bus and Local Bus for High End Microprocessor
466
I/O Subsystems
467
Memory Subsystems
467
Chapter 15 On-Circuit Emulation (Once)
471
Entering/Exiting ONCE Mode
471
Boundary Scan (Jtag)
472
Boundary Scan Architecture
472
Instruction Register
472
TAP Controller
472
Test Data Registers
472
Figure 15-1. Test Access Port Block Diagram
473
TAP Elements
473
Figure 15-2. TAP Controller State Diagram
474
Tap Registers
475
Instruction Register (IR)
475
Table 15-1. TAP Controller Pin Definitions
475
TAP Test Data Registers
476
Device Identification Register
476
Bypass Register
476
RUNBIST Register
477
Boundary-Scan Register
477
IEEE Required Instructions
478
Table 15-2. Boundary Scan Instruction Set
478
TAP Controller
479
Test Logic Reset State
480
Run-Test/Idle State
480
Select-DR-Scan State
480
Capture-DR State
480
Shift-DR State
481
Exit1-DR State
481
Pause-DR State
481
Exit2-DR State
481
Update-DR State
482
Select-IR Scan State
482
Capture-IR State
482
Shift-IR State
482
Exit1-IR State
483
Pause-IR State
483
Exit2-IR State
483
Update-IR State
483
Boundary-Scan Register
484
Table 15-3. Boundary Scan Register Bit Order
484
Example
485
Figure 15-3. JTAG Example
486
Figure 15-4. Timing Diagram Illustrating the Loading of Instruction Register
487
Boundary Scan Description Language Example
488
Figure 15-5. Timing Diagram Illustrating the Loading of Data Register
488
A.1 Core Architecture
495
A.2 Address Space Restrictions
496
A.2.1 Reserved Memory
496
A.2.2 Initialization Boot Record
496
A.2.3 Internal Data RAM
496
A.2.4 Instruction Cache
496
A.3 Data and Data Structure Alignment
497
A.4 Reserved Locations in Registers and Data Structures
498
A.5 Instruction Set
498
A.5.1 Instruction Timing
498
A.5.2 Implementation-Specific Instructions
499
A.6 Extended Register Set
499
A.7 Initialization
499
A.10 OTHER I960 Jx PROCESSOR IMPLEMENTATION-SPECIFIC FEATURES
500
A.8 Memory Configuration
500
A.9 Interrupts
500
A.10.1 Data Control Peripheral Units
501
A.10.2 Timers
501
A.10.3 Fault Implementation
501
A.11 Breakpoints
501
B.1 Instruction Reference by Opcode
505
Table B-1. Miscellaneous Instruction Encoding Bits
505
Table B-2. REG Format Instruction Encodings
506
Table B-3. COBR Format Instruction Encodings
510
Table B-4. CTRL Format Instruction Encodings
511
Table B-5. Cycle Counts for Sysctl Operations
511
Table B-6. Cycle Counts for Icctl Operations
512
Table B-7. Cycle Counts for Dcctl Operations
512
Table B-8. Cycle Counts for Intctl Operations
512
Table B-9. MEM Format Instruction Encodings
513
Table B-10. Addressing Mode Performance
514
C.1 General Instruction Format
517
Figure C-1. Instruction Formats
517
C.2 Reg Format
518
Table C-1. Instruction Field Descriptions
518
Figure 5-1. Machine-Level Instruction Formats
519
C.3 Cobr Format
519
Table C-2. Encoding of Src1 and Src2 in REG Format
519
Table C-3. Encoding of Src/Dst in REG Format
519
Table C-4. Encoding of Src1 in COBR Format
519
C.4 Ctrl Format
520
C.5 Mem Format
520
Table C-5. Encoding of Src2 in COBR Format
520
C.5.1 MEMA Format Addressing
521
Table C-6. Addressing Modes for MEM Format Instructions
521
C.5.2 MEMB Format Addressing
522
Table C-7. Encoding of Scale Field
522
Figure D-1. AC (Arithmetic Controls) Register
527
Figure D-2. PC (Process Controls) Register
528
Figure D-3. Procedure Stack Structure and Local Registers
529
Table D-1. Register and Data Structures
529
Figure D-4. System Procedure Table
530
Figure D-5. PFP (Previous Frame Pointer) Register (R0
531
Figure D-6. Fault Table and Fault Table Entries
532
Figure D-7. Fault Record
533
Figure D-8. TC (Trace Controls) Register
534
Figure D-9. BPCON (Breakpoint Control) Register
534
Figure D-10. DAB (Data Address Breakpoint) Register Format
535
Figure D-11. IPB (Instruction Breakpoint) Register Format
535
Figure D-12. TMR0-1 (Timer Mode Register
536
Figure D-13. TCR0-1 (Timer Count Register
536
Figure D-14. TRR0-1 (Timer Reload Register
537
Figure D-15. Interrupt Table
538
Figure D-16. Storage of an Interrupt Record on the Interrupt Stack
539
Figure D-17. ICON (Interrupt Control) Register
540
Figure D-18. IMAP0-IMAP2 (Interrupt Mapping) Registers
541
Figure D-19. IMSK (Interrupt Mask) Registers
542
Figure D-20. Interrupt Pending (IPND) Register
543
Figure D-21. Initial Memory Image (IMI) and Process Control Block (PRCB
544
Figure D-22. Process Control Block Configuration Words
545
Figure D-23. Control Table
546
Figure D-24. IEEE 1149.1 Device Identification Register
547
Figure D-25. PMCON Register Bit Description
547
Figure D-26. BCON (Bus Control) Register
548
Figure D-27. DLMCON (Default Logical Memory Configuration) Register
548
Figure D-28. LMADR0:1 Logical Memory Template Starting Address Registers
549
Figure D-29. LMMR0:1 (Logical Memory Mask Registers
549
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