User Manuals: Intel i960 Jx RISC Processor

Manuals and User Guides for Intel i960 Jx RISC Processor. We have 1 Intel i960 Jx RISC Processor manual available for free PDF download: Developer's Manual

Intel i960 Jx Developer's Manual

Intel i960 Jx Developer's Manual (578 pages)

Microprocessor

Brand: Intel | Category: Computer Hardware | Size: 3 MB

Table of Contents

Table of Contents
3
CHAPTER 1 Product Features

28
- Instruction Cache
  28
  - Data Cache
    28
  - On-Chip (Internal) Data RAM
    28
- Local Register Cache
  29
  - Interrupt Controller
    29
  - Timer Support
    30
  - Memory-Mapped Control Registers (MMR)
    30
CHAPTER 14 External Bus

30
- Complete Fault Handling and Debug Capabilities
  31
- About this Manual
  31
  - Notation and Terminology
    32
  - Reserved and Preserved
    32
  - Register Names
    33
  - Representing Numbers
    33
  - Specifying Bit and Signal Values
    33
- Related Documents
  34
- Table 1-1. Register Terminology Conventions
  34
- Data Types
  37
- Figure 2-1. Data Types and Ranges
  37
Chapter 2

38
- Integers
  38
- Ordinals
  38
- Bits and Bit Fields
  39
- Triple- and Quad-Words
  39
- Register Data Alignment
  39
- Literals
  40
- Bit and Byte Ordering in Memory
  40
  - Bit Ordering
    40
  - Byte Ordering
    40
  - Table 2-1. Memory Contents for Little and Big Endian Example
    41
  - Table 2-2. Byte Ordering for Little and Big Endian Accesses
    41
  - Figure 2-2. Data Placement in Registers
    42
  - Table 2-3. Memory Addressing Modes
    42
  - Absolute
    43
  - Register Indirect
    43
  - Index with Displacement
    44
  - IP with Displacement
    44
  - Addressing Mode Examples
    44
  - Overview
    49
Chapter 3 Registers and Literals as Instruction Operands

49
Chapter 4

64
Appendix A Instruction Cache

78
Chapter 5

87
- Assembly Language Format
  87
- Table 5-1. Instruction Encoding Formats
  88
- Instruction Operands
  89
- Instruction Groups
  90
  - Table 5-2. 80960Jx Instruction Set
    90
  - Data Movement
    91
    
    Load and Store Instructions
    91
  - Move
    92
    
    Load Address
    92
  - Select Conditional
    92
    
    Table 5-3. Arithmetic Operations
    93
    
    Add, Subtract, Multiply, Divide, Conditional Add, Conditional Subtract
    94
    
    Remainder and Modulo
    94
    
    Shift, Rotate and Extended Shift
    95
    
    Extended Arithmetic
    96
    
    Logical
    96
  - Bit, Bit Field and Byte Operations
    97
    
    Bit Operations
    97
    
    Bit Field Operations
    97
  - Comparison
    98
    
    Compare and Conditional Compare
    98
    
    Compare and Increment or Decrement
    99
    
    Test Condition Codes
    99
  - Branch
    100
    
    Unconditional Branch
    100
    
    Conditional Branch
    101
  - Compare and Branch
    101
  - Call/Return
    102
    
    Faults
    103
  - Atomic Instructions
    104
  - Debug
    104
  - Processor Management
    105
- Performance Optimization
  106
  - Instruction Optimizations
    106
    
    Load / Store Execution Model
    106
    
    Compare Operations
    106
    
    Microcoded Instructions
    107
    
    Multiply-Divide Unit Instructions
    107
    
    Multi-Cycle Register Operations
    107
    
    Simple Control Transfer
    108
    
    Memory Instructions
    108
    
    Unaligned Memory Accesses
    109
  - Miscellaneous Optimizations
    109
    
    Masking of Integer Overflow
    109
    
    Avoid Using PFP, SP, R3 as Destinations for MDU Instructions
    109
    
    Execute in Imprecise Fault Mode
    110
Chapter 6 Notation

113
- Alphabetic Reference
  114
- Mnemonic
  114
- Format
  114
- Description
  115
- Action
  115
  - Table 6-1. Pseudo-Code Symbol Definitions
    116
  - Table 6-2. Faults Applicable to All Instructions
    116
  - Example
    117
  - Faults
    117
- Table 6-3. Common Faulting Conditions
  117
- Opcode and Instruction Format
  118
- See also
  118
- Side Effects
  118
- Notes
  118
- Instructions
  118
  - Add<CC>
    119
  - Table 6-4. Condition Code Mask Descriptions
    119
  - Table 6-5. Condition Code Mask Descriptions
    120
  - Addc
    122
  - Addi, Addo
    123
  - Alterbit
    124
  - And, Andnot
    125
  - Atadd
    126
  - Atmod
    127
  - Bal, Balx
    129
  - Bbc, Bbs
    131
  - Branch<CC>
    133
  - Bswap
    135
CHAPTER 7 Call

136
- Calls
  137
- Callx
  139
- Chkbit
  141
- Clrbit
  142
- Cmpdeci, Cmpdeco
  143
- Table 6-6. Condition Code Settings
  143
- Cmpinci, Cmpinco
  144
- Table 6-7. Condition Code Settings
  144
- Compare
  145
- Table 6-8. Condition Code Settings
  145
- COMPARE and Branch<CC>
  147
- Table 6-9. Condition Code Mask Descriptions
  148
- Concmpi, Concmpo
  150
  - Table 6-10. Concmpo Example: Register Ordering and CC
    151
  - Table 6-11. Dcctl Operand Fields
    152
  - Figure 6-1. Dcctl Src1 and Src/Dst Formats
    
    153
  - Figure 6-4. Icctl Src1 and Src/Dst Formats
    
    171
  - Table 6-16. ICCTL Status Values and Instruction Cache Parameters
    172
  - Figure 6-5. Store Instruction Cache to Memory Output Format
    173
  - Figure 6-6. I-Cache Set Data, Tag and Valid Bit Formats
    174
  - Intctl
    178
  - Intdis
    180
  - Inten
    181
  - Load
    182
  - Mark
    186
  - Modac
    187
  - Modi
    188
  - Modify
    189
  - Modpc
    190
  - Modtc
    192
  - Move
    193
  - Muli, Mulo
    196
  - Nand
    197
  - Not, Notand
    199
  - Notbit
    200
  - Notor
    201
  - Or, Ornot
    202
  - Remi, Remo
    203
  - Rotate
    206
  - Scanbit
    207
  - Scanbyte
    208
    
    Sel<CC>
    209
    
    Table 6.17. Condition Code Mask Descriptions
    209
  - Setbit
    211
  - Shift
    212
  - Spanbit
    215
  - Store
    216
  - Subc
    220
  - Sub<CC>
    221
  - Subi, Subo
    224
  - Syncf
    225
  - Figure 6-7. Src1 Operand Interpretation
    226
  - Table 6-18. Sysctl Field Definitions
    226
  - Figure 6-8. Src/Dst Interpretation for Breakpoint Resource Request
    227
  - Table 6-19. Cache Mode Configuration
    227
  - Table 6-20. Condition Code Mask Descriptions
    230
  - Test<CC>
    230
  - Xnor, Xor
    232
    
    Call and Return Mechanism
    236
    
    Local Registers and the Procedure Stack
    236
  - Figure 7-1. Procedure Stack Structure and Local Registers
    237
  - Local Register and Stack Management
    238
    
    Frame Pointer
    238
    
    Stack Pointer
    238
    
    Considerations When Pushing Data Onto the Stack
    238
    
    Considerations When Popping Data off the Stack
    239
    
    Previous Frame Pointer
    239
    
    Return Type Field
    239
  - Call and Return Action
    239
    
    Call Operation
    240
    
    Return Operation
    241
  - Return Instruction Pointer
    239
  - Caching Local Register Sets
    241
    
    Reserving Local Register Sets for High Priority Interrupts
    242
    
    Figure 7-2. Frame Spill
    243
    
    Figure 7-3. Frame Fill
    244
  - Mapping Local Registers to the Procedure Stack
    245
  - Modifying the Pfp Register
    245
  - Parameter Passing
    246
  - Local Calls
    248
  - System Calls
    249
    
    System Procedure Table
    249
    
    Figure 7-4. System Procedure Table
    250
    
    Procedure Entries
    251
    
    Supervisor Stack Pointer
    251
    
    Table 7-1. Encodings of Entry Type Field in System Procedure Table
    251
    
    Trace Control Bit
    251
    
    System Call to a Local Procedure
    252
    
    System Call to a Supervisor Procedure
    252
  - Interrupt and Fault Calls
    253
  - User and Supervisor Stacks
    253
  - Figure 7-5. Previous Frame Pointer Register (PFP) (R0)
    254
  - Returns
    254
  - Branch-And-Link
    255
  - Table 7-2. Encoding of Return Status Field
    255
- Figure 6-2. Store Data Cache to Memory Output Format
  154
- Table 6-12. DCCTL Status Values and D-Cache Parameters
  154
- Figure 6-3. D-Cache Tag and Valid Bit Formats
  155
- DIVI, Divo
  159
- Ediv
  160
- Emul
  161
- Eshro
  162
- Extract
  163
- Fault<CC>
  164
- Table 6-13. Condition Code Mask Descriptions
  164
- Flushreg
  166
- Fmark
  167
- Halt
  168
- Table 6-15. Icctl Operand Fields
  170
Chapter 8

259
- Fault Handling Overview
  259
- Figure 8-1. Fault-Handling Data Structures
  259
- Fault Types
  261
- Fault Table
  262
- Figure 8-2. Fault Table and Fault Table Entries
  263
- Stack Used in Fault Handling
  264
  - Fault Record
    264
  - Fault Record Description
    265
  - Figure 8-3. Fault Record
    265
  - Fault Record Location
    266
  - Figure 8-4. Storage of the Fault Record on the Stack
    266
- Multiple and Parallel Faults
  267
- Fault Handling Procedures
  270
- Fault Handling Action
  274
  - Table 8-2. Fault Control Bits and Masks
    274
  - Local Fault Call
    275
  - System-Local Fault Call
    275
  - System-Supervisor Fault Call
    275
  - Faults and Interrupts
    276
- Precise and Imprecise Faults
  277
  - Asynchronous Faults
    277
  - No Imprecise Faults (Ac.nif) Bit
    278
  - Controlling Fault Precision
    278
- Fault Reference
  279
  - ARITHMETIC Faults
    280
  - CONSTRAINT Faults
    281
  - OPERATION Faults
    282
    
    OVERRIDE Faults
    284
    
    PARALLEL Faults
    285
  - PROTECTION Faults
    286
  - TRACE Faults
    287
  - TYPE Faults
    290
Chapter 9 Trace Controls

293
Chapter 10

314
Chapter 11

329
Chapter 12

373
- Reset State Operation
  373
- Figure 12-2. Cold Reset Waveform
  374
- Table 12-1. Reset States
  375
- Table 12-2. Register Values after Reset
  375
- Self Test Function (STEST, FAIL)
  376
  - The STEST Pin
    377
  - External Bus Confidence Test
    377
  - The Fail Pin (FAIL)
    377
  - IMI Alignment Check and System Error
    378
  - FAIL Code
    378
  - Figure 12-3. FAIL Sequence
    378
- Architecturally Reserved Memory Space
  379
- Device Identification on Reset
  392
  - Reinitializing and Relocating Data Structures
    392
  - Figure 12-8. IEEE 1149.1 Device Identification Register
    392
- Startup Code Example
  393
- System Requirements
  404
  - Input Clock (CLKIN)
    404
  - Power and Ground Planes
    405
  - Decoupling Capacitors
    406
  - I/O Pin Characteristics
    406
    
    Figure 12-10. Reducing Characteristic Impedance
    406
    
    Output Pins
    407
    
    Table 12-7. Input Pins
    407
  - High Frequency Design Considerations
    408
  - Line Termination
    408
  - Latchup
    409
  - Figure 12-11. Series Termination
    409
  - Figure 12-12. AC Termination
    409
  - Interference
    410
  - Figure 12-13. Avoid Closed-Loop Signal Paths
    411
CHAPTER 13 Memory Attributes

415
Chapter 15 On-Circuit Emulation (Once)

471
- Entering/Exiting ONCE Mode
  471
- Boundary Scan (Jtag)
  472
  - Boundary Scan Architecture
    472
    
    Instruction Register
    472
    
    TAP Controller
    472
    
    Test Data Registers
    472
    
    Figure 15-1. Test Access Port Block Diagram
    473
    
    TAP Elements
    473
    
    Figure 15-2. TAP Controller State Diagram
    474
- Tap Registers
  475

Advertisement

Advertisement

Related Products

Intel Categories

Motherboard Computer Hardware Server

Desktop

Desktop Server Board

More Intel Manuals