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The branch-and-link (
bal
and
The entire internal register cache contents can be copied to the external procedure stack through the
instruction.
Section 6.2.30, flushreg (pg. 6-54)
flushreg
"MODIFYING THE PFP REGISTER" (pg. 7-11)
used.
To decrease interrupt latency, software can reserve a number of frames in the local register cache
solely for high priority interrupts (interrupted state and process priority greater than or equal to 28).
The remaining frames in the cache can be used by all code, including high-priority interrupts.
When a frame is reserved for high-priority interrupts, the local registers of the code interrupted by
a high-priority interrupt can be saved to the local register cache without causing a frame flush to
memory, providing the local register cache is not already full. Thus, the register allocation for the
implicit interrupt call does not incur the latency of a frame flush.
Software can reserve frames for high-priority interrupt code by writing bits 10 through 8 of the
register cache configuration word in the PRCB. This value indicates the number of free frames
within the register cache that can be used by high-priority interrupts only. Any attempt by
non-critical code to reduce the number of free frames below this value results in a frame flush to
external memory. The free frame check is performed only when a frame is pushed, which occurs
only for an implicit or explicit call. The following pseudo-code illustrates the operation of the
register cache when a frame is pushed:
frames_for_non_critical = 7- RCW[10:8];
if (interrupt_request)
set_interrupt_handler_PC;
push_frame;
number_of_frames = number_of_frames + 1;
if (number_of_frames = 8) {
else if ( number_of_frames = (frames_for_non_critical + 1) &&
(PC.priority < 28 || PC.state != interrupted) ) {
The valid range for the number of reserved free frames is 0 to 7. Setting the value to 0 reserves no
frames for exclusive use by high-priority interrupts. Setting the value to 1 reserves 1 frame for
high-priority interrupts and 6 frames to be shared by all code. Setting the value to 7 causes the register
cache to become disabled for non-critical code. When the number of reserved high-priority frames
exceeds the allocated size of the register cache, the entire cache is reserved for high-priority interrupts.
In that case, all low-priority interrupts and procedure calls cause frame spills to external memory.
balx
) instructions do not cause the local registers to be stored.
offers a practical example when
Example 4-1. Register Cache Operation
flush_register_frame(oldest_frame);
number_of_frames = number_of_frames - 1; }
flush_register_frame(oldest_frame);
number_of_frames = number_of_frames - 1; }
CACHE AND ON-CHIP DATA RAM
explains the instruction and
flushreg
section 7.2,
must be
4
4-3
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