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CONSIDERATIONS FOR WRITING PORTABLE CODE
A.8
MEMORY CONFIGURATION
The i960 Jx processors employ Physical Memory Control (PMCON) and Logical Memory
Control (LMCON) registers to control bus width, byte order and the data cache. This capability is
analogous to the MCON register scheme employed by the i960 Cx processor. Memory
configurations, like the bus control unit, are implementation specific.
A.9
INTERRUPTS
The i960 architecture defines the interrupt servicing mechanism. This includes priority definition,
interrupt table structure and interrupt context switching that occurs when an interrupt is serviced.
The core architecture does not define the means for requesting interrupts (external pins, software,
etc.) or for posting interrupts (i.e., saving pending interrupts).
The method for requesting interrupts depends on the implementation. The i960 Jx processors have
an interrupt controller that manages nine external interrupt pins. The organization of these pins
and the registers of the interrupt controller are implementation specific. Code that configures the
interrupt controller is not directly portable to other i960 implementations.
On the i960Jx processors, interrupts may also be requested in software with the
This instruction and the software request mechanism are implementation specific.
Posting interrupts is also implementation specific. Different implementations may optimize
interrupt posting according to interrupt type and interrupt controller configuration. A pending
priorities and pending interrupts field is provided in the interrupt table for interrupt posting.
However, the i960 Jx processors post hardware-requested interrupts internally in the IPND
register instead. Code that requests interrupts by setting bits in the pending priorities and pending
interrupts field of the interrupt table is not portable. Also, application code that expects interrupts
to be posted in the interrupt table is not object-code portable to all i960-based products.
The i960 Jx processors do not store a resumption record for suspended instructions in the interrupt
or fault record. Portable programs must tolerate interrupt stack frames with and without these
resumption records.
A.10 OTHER i960 Jx PROCESSOR IMPLEMENTATION-SPECIFIC FEATURES
Subsections that follow describe additional implementation-specific features of the i960 Jx
processors. These features do not relate directly to application code portability.
A-6
sysctl
instruction.
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