Table 14-8. Summary Of N-Word Load And Store Accesses (N = 1, 2, 3, 4) - Intel i960 Jx Developer's Manual

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EXTERNAL BUS
Table 14-8. Summary of n -Word Load and Store Accesses ( n = 1, 2, 3, 4)
Address Offset
from Natural
Accesses on 8-Bit
Boundary in
Bus (WIDTH1:0=00)
Bytes
+0 (aligned)
n burst(s) of 4 bytes
( n =1, 2, 3, 4)
+1 ( n =1, 2, 3, 4)
byte access
burst of 2 bytes
+5 ( n = 2, 3, 4)
n -1 burst(s) of 4 bytes
+9 ( n = 3, 4)
byte access
+13 ( n = 3, 4)
+2 ( n =1, 2, 3, 4)
burst of 2 bytes
n -1 burst(s) of 4 bytes
+6 ( n = 2, 3, 4)
burst of 2 bytes
+10 ( n = 3, 4)
+14 ( n = 3, 4)
+3 ( n =1, 2, 3, 4)
byte access
n -1 burst(s) of 4 bytes
+7 ( n = 2, 3, 4)
burst of 2 bytes
+11 ( n = 3, 4)
byte access
+15 ( n = 3, 4)
+4 ( n = 2, 3, 4)
n burst(s) of 4 bytes
+8 ( n = 3, 4)
+12 ( n = 3, 4)
14-24
Accesses on 16 Bit Bus
(WIDTH1:0=01)
case n =1:
burst of 2 short words
case n =2:
burst of 4 short words
case n =3:
burst of 4 short words
burst of 2 short words
case n =4:
2 bursts of 4 short words
byte access
short-word access
n -1 burst(s) of 2 short words
byte access
short-word access
n -1 burst(s) of 2 short words
short-word access
byte access
n -1 burst(s) of 2 short words
short-word access
byte access
n burst(s) of 2 short words
Accesses on 32 Bit
Bus
(WIDTH1:0=10)
burst of n word(s)
byte access
short-word access
n -1 word
access(es)
byte access
short-word access
n -1 word
access(es)
short-word access
byte access
n -1 word
access(es)
short-word access
byte access
n word access(es)

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