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TEST FEATURES
15.2
BOUNDARY SCAN (JTAG)
The i960 Jx processor provides test features compatible with IEEE Standard Test Access Port and
Boundary Scan Architecture (IEEE Std. 1149.1). JTAG ensures that components function
correctly, connections between components are correct, and components interact correctly on the
printed circuit board.
15.2.1
Boundary Scan Architecture
Boundary scan test logic consists of a Boundary-Scan register and support logic. These are
accessed through a Test Access Port (TAP). The TAP provides a simple serial interface that allows
all processor signal pins to be driven and/or sampled, thereby providing the direct control and
monitoring of processor pins at the system level.
This mode of operation is valuable for design debugging and fault diagnosis since it permits
examination of connections not normally accessible to the test system. The following subsections
describe the boundary scan test logic elements: TAP controller, Instruction register, Test Data
registers and TAP elements.
15.2.1.1
TAP Controller
The TAP controller is a 16 state machine, which provides the internal control signals to the
instruction register and the test data registers. The state of the TAP controller is determined by the
logic present on the Test Mode Select (TMS) pin on the rising edge of TCK. See
the state diagram of the TAP controller.
15.2.1.2
Instruction Register
The instruction register (IR) holds instruction codes shifted through the Test Data Input (TDI) pin.
The instruction codes are used to select the specific test operation to be performed and the test data
register to be accessed.
15.2.1.3
Test Data Registers
The four test data registers are:
•
Device ID register (see
•
Bypass register (see
section 15.3.2.2, "Bypass Register" (pg.
•
RUNBIST register (see
•
Boundary-Scan register (see
15-2
section 15.3.2.1, "Device Identification Register" (pg.
section 15.3.2.3, "RUNBIST Register" (pg.
section 15.3.2.4, "Boundary-Scan Register" (pg.
Figure 15-2
15-6)).
15-6)).
15-7)).
15-7)).
for
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