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INTERRUPTS
11.9.4.1
Avoiding Certain Destinations for MDU Operations
Typically, when delivering an interrupt, the processor attempts to push the first four local registers
(pfp, sp, rip, and r3) onto the local register cache as early as possible. Because of
register-interlock, this operation is stalled until previous instructions return their results to these
registers. In most cases, this is not a problem; however, in the case of instructions performed by the
Multiply/Divide Unit (
divo
many cycles waiting for the result and unable to proceed to the next step of interrupt delivery.
Interrupt latency can be improved by avoiding the first four local registers as the destination for a
Multiply/Divide Unit operation. (Registers pfp, sp, and rip should be avoided for general
operations as these are used for procedure linking.)
11.9.4.2
Masking Integer Overflow Faults for syncf
The i960 core architecture requires an implicit
handler can be dispatched first, if necessary. The
complete if a multi-cycle multiply or divide instruction was issued previously and
integer-overflow faults are unmasked (allowed to occur). Interrupt latency can be improved by
masking integer-overflow faults, which allows the implicit
time.
11-42
,
divi
,
ediv
,
modi
,
remo
, and
before delivering an interrupt so that a fault
syncf
syncf
remi
), the processor could be stalled for
can require a number of cycles to
syncf
to complete in much shorter
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