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EXTERNAL BUS
Figure 14-3
also shows a typical timing diagram for a non-burst, 32-bit write transaction. For the
write operation, W/R and DT/R are high to denote the direction of the data flow. The D/C pin is
high since instruction code cannot be written. During the Tw/Td state, the processor drives data on
the bus, waiting to sample RDYRCV low to terminate the transfer. The figure shows RDYRCV
assertion by external logic, so this state is a data state and the processor enters the recovery state.
At the end of a write, notice that the write data is driven during Tr and any subsequent Ti states.
After a write, the processor will drive write data until the next Ta state. See
section 14.2.4, "Bus
and Control Signals During Recovery and Idle States" (pg. 14-22)
for details.
14.2.3.3
Burst Transactions
A burst access is an address cycle followed by two to four data transfers. The i960 Jx micropro-
cessor uses burst transactions for instruction fetching and accessing system data structures.
Therefore, a system design incorporating an i960 Jx microprocessor must support burst transac-
tions. Burst accesses can also result from instruction references to data types which exceed the
width of the bus.
Maximum burst size is four data transfers, independent of bus width. A byte-wide bus has a
maximum burst size of four bytes; a word-wide bus has a maximum of four words. For an 8- or
16-bit bus, this means that some bus requests may result in multiple burst accesses. For example, if
a quad word load request (e.g., ldq instruction) is made to an 8-bit data region, it results in four,
4-byte, burst accesses. (See
Table 14-6 (pg.
14-23).
Burst accesses on a 32-bit bus are always aligned to even-word boundaries. Quad-word and
triple-word accesses always begin on quad-word boundaries (A3:2=00); double-word transfers
always begin on double-word boundaries (A2=0); single-word transfers occur on single word
boundaries.
Figure 14-4
shows burst, stop and start addresses for a 32-bit bus.
14
14-11
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