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TEST FEATURES
15.3.6
Boundary-Scan Register
The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and
HIGHZ pins.
Table 15-2
shows the bit order of the i960 Jx processor Boundary-Scan register. All table cells that
contain "CTL" select the direction of bidirectional pins or HIGHZ output pins. If a "1" is loaded
into the control cell, the associated pin(s) are HIGHZ or selected as input.
Table 15-3. Boundary Scan Register Bit Order
Input/
Bit
Signal
Output
0
RDYRCV (TDI)
1
HOLD
2
XINT0
3
XINT1
4
XINT2
5
XINT3
6
XINT4
7
XINT5
8
XINT6
9
XINT7
10
NMI
11
FAIL
12
ALE
13
WIDTH/HLTD1
14
WIDTH/HLTD0
15
A2
16
A3
17
CONTROL1
Enable cell
18
CONTROL2
Enable cell
19
BLAST
20
D/C
21
ADS
22
W/R
23
DT/R
1. Enable cells are active low.
15-14
Bit
Signal
I
24
DEN
I
25
HOLDA
I
26
ALE
LOCK/ONCE
I
27
cell
I
28
LOCK/ONCE
I
29
BSTAT
I
30
BE0
I
31
BE1
I
32
BE2
I
33
BE3
I
34
AD31
I
35
AD30
O
36
AD29
1
37
AD28
1
38
AD27
O
39
AD26
O
40
AD25
1
41
AD24
1
42
AD23
O
43
AD22
O
44
AD21
O
45
AD20
O
46
AD19
O
47
AD18
Input/
Bit
Signal
Output
O
48
AD17
O
49
AD16
O
50
AD15
1
Enable cell
51
AD14
I/O
52
AD13
O
53
AD12
O
54
AD cells
O
55
AD11
O
56
AD10
O
57
AD9
I/O
58
AD8
I/O
59
AD7
I/O
60
AD6
I/O
61
AD5
I/O
62
AD4
I/O
63
AD3
I/O
64
AD2
I/O
65
AD1
I/O
66
AD0
I/O
67
CLKIN
I/O
68
RESET
STEST
I/O
69
(TDO)
I/O
I/O
Input/
Output
I/O
I/O
I/O
I/O
I/O
I/O
Enable
1
cell
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
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